Glossary
Every specialist or coined term this site uses, defined once, with a link to the page that treats it properly. If you arrived on a deep page and hit a word like trit-trie or TMAJ3 cold, this is the page that was missing.
Definitions
Balanced ternary
Base 3 written with the digit set −1, 0, +1 rather than 0, 1, 2. Each position is a power of three and a digit may add its place value, subtract it, or contribute nothing. Every integer has exactly one representation, and no sign bit is needed.
Trit
One balanced ternary digit, taking the value −1, 0 or +1. A trit carries log₂3 ≈ 1.585 bits of information, so three trits hold 27 distinct values.
See: Ternary calculator
Setun
The balanced ternary computer built at Moscow State University in 1958, using magnetic transformer cores rather than transistors. It proved balanced ternary works in hardware; what it lacked was a naturally three-state device. Each trit was stored in a PAIR of ferrite cores wired in tandem, because a square-loop core is bistable and Setun's were not even ideally square — so the three states were built from two-state parts rather than read off one.
See: Balanced ternary vs binary · FAQ
THATTE stack
The complete photonic balanced-ternary computing system covered by twelve patent specifications filed with the Indian Patent Office in 2026, from the nanotube device up through gates, processor, memory, security, compiler and operating system.
See: Patents · Technology
SWCNT@MWCNT
A single-walled carbon nanotube inside a multi-walled one — the coaxial geometry of the THATTE switching device. The notation “A@B” is the standard way of writing one nanotube nested inside another.
See: Thatte1 — the device
Chirality
The roll-up vector of a carbon nanotube, which decides whether it is metallic or semiconducting. CVD growth produces a distribution of chiralities and only the target metallic armchair chirality works, which makes chirality yield the first of the three hard problems.
NEGF
Non-equilibrium Green’s function: the quantum transport formalism used to compute current through a nanoscale device from first principles. NEGF simulation is what confirmed trit switching in the THATTE device at room temperature.
See: Technology · SPICE verification
CNFET
Carbon nanotube field-effect transistor. The Stanford CNFET compact model is the community standard for circuit simulation, and it was built for a semiconducting-channel transistor rather than for a coaxial metallic switch — which is why this project wrote its own model.
See: RAVAN compact model
RAVAN
The project’s own physics-based compact model for the THATTE device, written from first principles rather than adapted from a transistor model built for different physics.
RTN
Random telegraph noise: discrete, step-like jumps in device current caused by single charges trapping and detrapping. In a three-state device the noise budget is tighter than in a two-state one, which is why coaxial shielding is quantified rather than assumed.
TINV
Ternary inverter: the gate that negates a trit, mapping −1 to +1, 0 to 0 and +1 to −1. In balanced ternary this single gate is the whole of negation.
TMIN / TMAX
Ternary minimum and maximum: the three-valued counterparts of AND and OR. TMIN returns the smaller of two trits, TMAX the larger.
TMAJ3
The three-input ternary majority gate. With three inputs each taking three values its truth table has 27 entries, all of which were verified in SPICE against the gate as built.
See: SPICE verification
PANINI
The codename of the balanced ternary processor architecture in the THATTE stack — register file, ALU and pipeline built around trits rather than bits.
See: Thatte3 — processor and T3ISA · PANINI ternary SRAM cell
T3ISA
The instruction set architecture for PANINI. Instructions are a fixed 27-trit word — 27 being 3³ — with three-trit register fields, so 27 registers are addressed exactly.
See: T3ISA explorer · Thatte3
ManiT
The typed systems programming language of the stack, in which three-valued logic is native rather than emulated. Its compiler is maniTC, released under AGPL-3.0.
THATTEOS
The microkernel operating system written entirely in ManiT, whose privilege model is one trit deep: kernel, supervisor and user are −1, 0 and +1, and a permission check is the ternary minimum function.
See: Open source · THATTE-OS microkernel
Trit-trie
A prefix tree over balanced ternary, branching three ways at every node instead of two. The same key space is covered in log₃ rather than log₂ steps — about 63 % of the depth of a binary trie.
TritFS
The ternary file system of THATTEOS, whose address space is expressed in trits rather than bits.
See: TritFS address space
GF(3)
The finite field with three elements, whose arithmetic is exactly balanced ternary addition and multiplication modulo 3. Because multiplication by a field element is a permutation of −1, 0, +1, much of a GF(3) arithmetic network is interconnect rather than active devices.
DPA
Differential power analysis: a side-channel attack that recovers a key by correlating secret-dependent data with measured power consumption.
DFT / BIST
Design for test and built-in self-test: the on-chip structures that make a manufactured part testable, and that let it test itself. A logic family with three states needs its own, because binary scan and test patterns do not transfer.
See: Thatte5 — DFT/BIST
Qutrit
A three-level quantum system, the ternary counterpart of a qubit. It is not the same thing as a classical trit: a qutrit holds a superposition of its three basis states.
See: Thatte12 — temperature-modal qutrit device · The wrong kind of quantum
Ternary NPU
A neural processing unit whose weights and activations are trits. Ternary weight quantisation is already standard practice in binary machine learning, which makes a natively ternary accelerator an unusually direct fit.
If You Are New to All of This
Read how it works first: it starts from the number system and builds up to the operating system without assuming any of the vocabulary above. Balanced ternary vs binary is the shorter comparison, and the calculator is the fastest way to get a feel for the arithmetic. The twelve patents are the formal record, and the released code is the part you can run tonight.
Full Technical Brief Available Under NDA
Simulation data, quantum transport results, fabrication specifications, and complete patent claims are shared under mutual NDA only.
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