SPICE Verification: Proving the Ternary Gate Library Works
How we used ngspice with the Stanford CNFET model to verify every gate in the library — from inverter symmetry to a 27-entry majority gate truth table.
maniTLab introduces a complete balanced ternary computing system — from a novel carbon nanotube FET device to a fully compiled microkernel operating system. Nine patents covering every layer of the stack, filed with the Indian Patent Office.
From a single transistor to a running operating system — every layer of the ternary computing stack is patented, implemented, and verified.
Balanced ternary trie for efficient indexed storage and retrieval
Trit-addressed memory heap management and network buffer allocation
Boot loader, scheduler, interrupt handler, privilege domains — compiled and running
Lexer, parser, code generator targeting the balanced ternary instruction set
3-FET cyclic SRAM cell, modulo-3 clock generation, full ALU
TINV, TMIN2, TMAX3, TMAJ3 — SPICE-verified with Stanford CNFET model
Benzene precursor chemical vapor deposition, optimized for ternary symmetry
Current-direction encoding, RTN reduction via MWCNT coaxial shielding
SWCNT@MWCNT channel, GNR gate, symmetric switching at ±0.3 V threshold
All nine patents filed with the Indian Patent Office in March 2026. Complete specifications, drawings, and SPICE verification attached.
Hybrid SWCNT@MWCNT FET with GNR gate electrode, operating on three voltage rails (VDD/GND/VSS). Symmetrical switching at ±0.3 V threshold.
Current-direction encoding of three logic states. Random Telegraph Noise reduction through MWCNT coaxial shielding geometry.
Step-by-step chemical vapor deposition process using benzene as carbon source. Process optimized for ternary symmetry. Conception proven to 2006.
Full compiler for the T3ISA ternary instruction set: lexer, parser, and code generator. All three trit states verified in execution.
Complete operating system microkernel: boot loader, scheduler, interrupt handler, process manager, privilege domains. Compiled and executed.
TINV, TMIN2, TMAX3, TMAJ3 cells — fully SPICE-simulated using ngspice-44.2 with Stanford CNFET model. 27/27 truth table entries correct.
Novel 3-FET cyclic SRAM cell with three stable states. Modulo-3 clock generation. Cross-coupled nodes N1/N2 through all three voltage rails.
Trit-addressed resource allocation, memory heap management, and network buffers. Includes 128-entry ASCII-to-balanced-ternary encoding table.
Continuation of P8. Efficient balanced ternary trie for indexed storage, branching on three trit states at each node level.
The balanced ternary gate library was rigorously simulated using ngspice-44.2 with the Stanford University CNFET model (Deng & Wong 2007) on Debian 13, AMD EPYC 9334.
Every claim about symmetry, threshold voltage, leakage current, and truth table correctness is backed by reproducible simulation data.
Research notes, experiment findings, and technical deep-dives on balanced ternary computing.
How we used ngspice with the Stanford CNFET model to verify every gate in the library — from inverter symmetry to a 27-entry majority gate truth table.
Design decisions behind a balanced ternary microkernel — from privilege domains to the T3ISA syscall interface, and how the ManiT compiler makes it all compile.
The mathematical elegance of base-3, natural signed-number representation, and the physical case for three voltage levels in nanotube FET devices.