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Technical writeups, experiment logs, and design rationale from the development of the THATTE balanced ternary computing system.

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Hardware Theory Patent Thatte1

RAVAN: Why We Built Our Own Compact Model from First Principles

Generic MOSFET wrappers hide the real physics of novel devices. When your simulation gives a perfect 1.000 symmetry ratio, the question is not whether the device works — it is whether your model is telling you the truth. This is the story of replacing a borrowed model with one built from the ground up.

Read Post 2 April 2026 · 14 min read
RAVAN ModelVERIFIED
TransportLandauer
Temp range4 K – 1000 K+
Symmetry< 1.0 (realistic)
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17 Apr 2026

NEGF Quantum Transport: How We Proved the Device Works

The story of the NEGF simulation that confirmed the SWCNT@MWCNT device: ±74 µA trit currents, SNR > 2000, and the quantum mechanism behind photonic trit encoding.

Hardware Theory Patent Thatte1
15 Apr 2026

From 9 Provisionals to 6 Complete Specs: Consolidating the Patent Stack

How 9 provisional applications became 6 complete specifications — not just paperwork, but a deeper understanding of the architecture after the paradigm shift to photonic AC.

Patent Theory
13 Apr 2026

Why AC, Not DC: The Transmission Line Paradigm

The SWCNT is a transmission line, not a resistive switch. AC gives you three states for free. Why the entire photonic-ternary paradigm follows from abandoning the DC mindset.

Theory Hardware Patent Thatte1
2 Apr 2026

RAVAN: Why We Built Our Own Compact Model from First Principles

Why generic transistor models hide the real physics of novel devices, and how the RAVAN compact model replaces a MOSFET wrapper with Landauer transport, Fermi-Dirac statistics, and first-principles temperature dependence.

Hardware Theory Patent Thatte1
1 Apr 2026

RTN Shielding: Quantifying Noise Reduction in Coaxial CNT Channels

Random telegraph noise in nanoscale devices, why ternary devices have tighter noise margins, and what the NEGF simulation reveals about the SWCNT@MWCNT device's noise resilience.

Hardware Patent Thatte1
31 Mar 2026

ManiT Compiler: Why Ternary Needs Its Own Instruction Set

Why binary code cannot run on ternary hardware, the design space for a ternary ISA, and what compiling the THATTEOS kernel to 72 KB of .t3b binaries proved.

Software Patent Thatte6
30 Mar 2026

Fabrication Notes: CVD and Chirality Control in Carbon Nanotubes

The publicly known science of metallocene CVD, the chirality problem in CNT synthesis, and how a 2006 priority date anchors the THATTE fabrication patent.

Hardware Patent Thatte1
29 Mar 2026

TritFS: Designing a Filesystem for Ternary Storage

What changes when storage addresses use trits instead of bits — inode design, ternary bitmaps, trit-state journalling, and the ASCII encoding challenge in balanced ternary.

Software Patent Thatte4
28 Mar 2026

PANINI Processor: Designing a Ternary SRAM Cell

Why traditional 6T SRAM cannot store three states, what a 3-FET ternary memory cell achieves, and why compact SRAM is the most commercially valuable piece of the PANINI processor.

Hardware Patent Thatte3
27 Mar 2026

SPICE Verification: Proving the Ternary Gate Library Works

How we used NEGF quantum transport simulation to verify the SWCNT@MWCNT device and the ternary gate library. What the numbers mean and why they matter for real fabrication.

Hardware Patent Thatte2
26 Mar 2026

THATTE-OS: Building a Microkernel for Ternary Hardware

Design decisions behind a balanced ternary microkernel — from privilege domains to the T3ISA syscall interface. How the ManiT compiler makes it compile, and what a ternary boot sequence looks like.

Software Patent Thatte6
25 Mar 2026

Why Balanced Ternary? The Case Against Binary

The mathematical elegance of base-3, natural signed-number representation without two's complement, and the physical case for photonic trit encoding in SWCNT@MWCNT devices. Why now?

Theory Hardware
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