Technical writeups, experiment logs, and design rationale from the development of the THATTE balanced ternary computing system.
The balanced ternary software stack now has its paper: 13 pages on Zenodo, CC BY 4.0, with its own DOI — dual-backend equivalence on 18 of 20 programs, privilege checking as a ternary minimum, two honestly reported defects, and no performance claims for hardware that does not yet exist. The compiler and the kernel got DOIs of their own, and Software Heritage holds both repositories forever.
A balanced ternary computer was built at Moscow State University in 1958, produced in the dozens and used for real work. What stopped ternary hardware was not its arithmetic but its element base — ferrite cores are natively three-state and transistors are not. Three things have since changed, and one of them is a device.
Everybody publishes results. Almost nobody publishes the protocol they use to catch their own mistakes. This is mine: five checks applied to every derived number in the simulation stack, why the fourth one matters most, and four real errors it found in my own work.
The stack's evaluation, deposited on Zenodo with DOI 10.5281/zenodo.21894460: every shipped program compiled to two independent backends and compared byte for byte, 18 of 20 identical; two silent-wrong-answer defects reported as the finding; code DOIs and Software Heritage archives for the compiler and the kernel.
The complete software stack for balanced ternary computing goes open source: the ManiT language, the manitc compiler with LLVM and T3ISA backends and a cycle-accurate emulator, and the THATTEOS microkernel with shell and userspace — AGPL-3.0, with your compiled programs exempt and yours under any license.
The plan has always been to patent everything and then release it free. An account of what was built — from nanotube to operating system — why the patents matter for authorship rather than rent, and what happens after the international filings close in 2027.
Differential power analysis breaks cryptographic hardware by correlating power consumption with secret data. In binary, the leak is structural — 0 and 1 consume different power. In balanced ternary, trit +1 and trit −1 are power-identical. The attack surface does not exist.
Six patents, one coherent system. From two carbon nanotubes to a running balanced ternary operating system — what the THATTE stack is, why balanced ternary, and what it means to design a computing architecture from device physics to OS.
The three manufacturing obstacles that stand between NEGF-predicted device physics and a working chip — why they are coupled, what the field has tried, and what Patents Thatte1 and Thatte2 address.
The THATTE device is two carbon nanotubes. But it started as four layers, a semiconducting channel, and a DC gate. This is the story of the three paradigms that preceded the final design — and why physics, not preference, drove each transition.
How 9 provisional applications became 6 complete specifications — not just paperwork, but a deeper understanding of the architecture after the paradigm shift to photonic AC.
The SWCNT is a transmission line, not a resistive switch. AC gives you three states for free. Why the entire photonic-ternary paradigm follows from abandoning the DC mindset.
Why generic transistor models hide the real physics of novel devices, and how the RAVAN compact model replaces a MOSFET wrapper with Landauer transport, Fermi-Dirac statistics, and first-principles temperature dependence.
Random telegraph noise in nanoscale devices, why ternary devices have tighter noise margins, and what the NEGF simulation reveals about the SWCNT@MWCNT device's noise resilience.
Why binary code cannot run on ternary hardware, the design space for a ternary ISA, and what compiling the THATTEOS kernel to 72 KB of .t3b binaries proved.
The publicly known science of CVD, the chirality problem in CNT synthesis, and how a 2006 priority date anchors the THATTE fabrication patent.
What changes when storage addresses use trits instead of bits — inode design, ternary bitmaps, trit-state journalling, and the ASCII encoding challenge in balanced ternary.
Why traditional 6T SRAM cannot store three states, what a three-device cyclic current-mode SRAM cell achieves, and why compact SRAM is the most commercially valuable piece of the PANINI processor.
How we used NEGF quantum transport simulation to verify the SWCNT@MWCNT device and the ternary gate library. What the numbers mean and why they matter for real fabrication.
Design decisions behind a balanced ternary microkernel — from privilege domains to the T3ISA syscall interface. How the ManiT compiler makes it compile, and what a ternary boot sequence looks like.
The mathematical elegance of base-3, natural signed-number representation without two's complement, and the physical case for photonic trit encoding in SWCNT@MWCNT devices. Why now?
Simulation data, quantum transport results, fabrication specifications, and complete patent claims are shared under mutual NDA only.
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