Technical writeups, experiment logs, and design rationale from the development of the THATTE balanced ternary computing system.
Clock distribution consumes 30–40% of binary processor power. The THATTE processor eliminates this entirely: the gate photon that enables each SWCNT@MWCNT device IS the clock pulse. No crystal oscillator, no PLL, no H-tree, no clock buffers — and zero idle power by construction.
Clock distribution consumes 30–40% of binary processor power. The THATTE processor eliminates this entirely — the gate photon IS the clock. No crystal oscillator, no PLL, no H-tree, zero idle power, and a single-cycle three-way branch instruction.
Differential power analysis breaks cryptographic hardware by correlating power consumption with secret data. In binary, the leak is structural — 0 and 1 consume different power. In balanced ternary, trit +1 and trit −1 are power-identical. The attack surface does not exist.
Six patents, one coherent system. From two carbon nanotubes to a running balanced ternary operating system — what the THATTE stack is, why balanced ternary, and what it means to design a computing architecture from device physics to OS.
The three manufacturing obstacles that stand between simulation-confirmed device physics and a working chip — why they are coupled, what the field has tried, and what Patents Thatte1 and Thatte2 address.
The THATTE device is two carbon nanotubes. But it started as four layers, a semiconducting channel, and a DC gate. This is the story of the three paradigms that preceded the final design — and why physics, not preference, drove each transition.
The story of the NEGF simulation that verified the SWCNT@MWCNT device: ±74 µA trit currents at 0.5 V, SNR > 2000 (54 dB), and the quantum mechanism behind photonic trit encoding.
How 9 provisional applications became 6 complete specifications — not just paperwork, but a deeper understanding of the architecture after the paradigm shift to photonic AC.
The SWCNT is a transmission line, not a resistive switch. AC gives you three states for free. Why the entire photonic-ternary paradigm follows from abandoning the DC mindset.
Why generic transistor models hide the real physics of novel devices, and how the RAVAN compact model replaces a MOSFET wrapper with Landauer transport, Fermi-Dirac statistics, and first-principles temperature dependence.
Random telegraph noise in nanoscale devices, why ternary devices have tighter noise margins, and what the NEGF simulation reveals about the SWCNT@MWCNT device's noise resilience.
Why binary code cannot run on ternary hardware, the design space for a ternary ISA, and what compiling the THATTEOS kernel to 72 KB of .t3b binaries proved.
The publicly known science of metallocene CVD, the chirality problem in CNT synthesis, and how a 2006 priority date anchors the THATTE fabrication patent.
What changes when storage addresses use trits instead of bits — inode design, ternary bitmaps, trit-state journalling, and the ASCII encoding challenge in balanced ternary.
Why traditional 6T SRAM cannot store three states, what a three-device cyclic current-mode SRAM cell achieves, and why compact SRAM is the most commercially valuable piece of the PANINI processor.
How we used NEGF quantum transport simulation to verify the SWCNT@MWCNT device and the ternary gate library. What the numbers mean and why they matter for real fabrication.
Design decisions behind a balanced ternary microkernel — from privilege domains to the T3ISA syscall interface. How the ManiT compiler makes it compile, and what a ternary boot sequence looks like.
The mathematical elegance of base-3, natural signed-number representation without two's complement, and the physical case for photonic trit encoding in SWCNT@MWCNT devices. Why now?
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