Why Balanced Ternary?
The Case Against Binary

The Radix Problem

Binary computing was not inevitable. Early computers explored multiple number bases — decimal, octal, hexadecimal, and ternary — before binary became the dominant standard in the 1950s. The reasons were largely practical: transistors were, at the time, easiest to manufacture in a bistable configuration. On or off. Two states.

But there is a deeper mathematical question that was settled long before transistors existed: what is the most efficient radix for information encoding?

The answer, proven in 1959 by Stibitz and later formalised in information theory, is that the most efficient base — minimising the product of the number of symbols and the number of positions needed to represent a given range of values — is e ≈ 2.718. Since we must use integers, the closest is 3.

This means that base-3 is provably more information-dense than base-2. Each trit carries log₂(3) ≈ 1.585 bits of information. A binary digit carries 1 bit. For the same number of digit positions, a ternary system encodes 58.5% more information.

What Makes Balanced Ternary Special

Standard ternary uses digits {0, 1, 2}. Balanced ternary uses {−1, 0, +1}. The "balanced" refers to symmetry around zero, and this small change has profound consequences.

No Two's Complement

In binary, negative numbers require a representation convention. The near-universal choice is two's complement: to negate a number, flip all bits and add one. This works, but it introduces an asymmetry: in an n-bit two's complement system, the most negative number is −2ⁿ⁻¹ but the most positive is only 2ⁿ⁻¹ − 1.

In balanced ternary, negation is trivial: flip the sign of every trit. If +5 is represented as (+1)(−1)(−1) in balanced ternary (= 9 − 3 − 1 = 5), then −5 is simply (−1)(+1)(+1). No special representation. No asymmetry. No overflow edge cases.

Symmetric Arithmetic

Because balanced ternary is symmetric around zero, rounding is natural: round to the nearest trit by simply truncating — the maximum error is always at most half the weight of the least significant trit. In binary, rounding requires "round half up" or "round half to even" conventions to handle ties.

Comparison operations also become symmetric. In binary, checking a >= 0 requires sign-bit inspection (for signed integers) or is trivially true (for unsigned). In balanced ternary, the sign of a number is simply the most significant non-zero trit.

Historical Precedent: The Setun Computer

In 1958, Nikolay Brusentsov at Moscow State University built the Setun — the world's first balanced ternary computer. It used transformer cores in three states and ran until 1965. By all accounts, its arithmetic unit was simpler and more elegant than contemporary binary machines.

"The experience of operation of the Setun computer showed that the ternary system offers notable advantages: a simpler structure of arithmetic units, more convenient representation of negative numbers, and a higher efficiency of machine resources."

— N.P. Brusentsov, 1965

The Setun was eventually discontinued — not because ternary proved inferior, but because the global momentum behind binary computing made it impossible to source ternary components. Network effects, not physics, ended ternary computing in the 1960s.

The Physical Case: Three Voltage Levels

The most common objection to ternary computing is physical: "transistors are binary. They're on or off." This is approximately true for bulk silicon MOSFET devices, which have a high sub-threshold slope making the transition region sharp and narrow.

It is not true for carbon nanotube FETs (CNFETs).

CNFETs have several properties that make three-state operation natural:

• Near-ballistic transport: current can flow in either direction with equal symmetry
• Tunable threshold voltage through tube chirality and diameter — not just doping
• Ambipolar behaviour in some configurations — both electron and hole conduction
• High current drive for small cross-section: three states are well-separated

The THATTE device exploits this by using a SWCNT@MWCNT channel geometry. Three voltage rails — VDD (+1 V), GND (0 V), VSS (−1 V) — create three naturally stable operating regions. The GNR gate electrode is tuned to ±0.3 V threshold voltages, creating symmetric positive and negative switching.

The current direction — not just magnitude — encodes the trit state. This is the key insight: in a balanced ternary CNFET, logic and physics align perfectly. Current flowing towards drain: +1. Zero current: 0. Current flowing away from drain: −1.

The Power Efficiency Argument

Power consumption in digital circuits scales with switching activity and the number of transitions per operation. A ternary system can represent a wider range of values with fewer digit positions than a binary system of the same "width."

For a given computational workload, ternary arithmetic requires fewer operations (because each trit carries more information), which means fewer voltage transitions, which means less dynamic power. The lower device count for equivalent logic complexity also reduces leakage current in standby states.

This is not a small effect. For applications in the "dark silicon" regime — where modern chips cannot power all transistors simultaneously — reducing the transistor count per equivalent logic function is critical. Balanced ternary addresses this at the most fundamental level.

Why Now?

Binary computing is approaching fundamental physical limits. At sub-5 nm gate lengths, quantum tunnelling, thermal noise, and variability make further binary scaling extremely difficult. The industry is exploring novel materials (GaN, SiC, 2D materials) and novel architectures (near-memory computing, neuromorphic chips).

Carbon nanotube FETs have emerged as one of the most promising post-silicon transistor technologies. IBM, Stanford, and TSMC have all demonstrated CNFET circuits. The material science challenges are real, but CNFETs are approaching fabrication readiness.

This is exactly the moment to establish balanced ternary as the logic paradigm for CNFET-based computing. The THATTE patent stack does exactly that: it defines a complete system from device physics through operating system, designed from first principles around balanced ternary and carbon nanotube transistors.

The 2006 Connection

The core concept of the THATTE device — a three-state carbon nanotube transistor operating on three voltage rails with current-direction encoding — was conceived in 2006, predating the mainstream interest in CNFET-based ternary logic by nearly a decade.

A notarized affidavit (Exhibit A in Patent P3) documents this priority. The filing of nine patents in March 2026 represents the maturation of that 2006 concept into a complete, verified, compiled, running balanced ternary computing system.

The Setun proved that balanced ternary works. The THATTE stack proves it works at the nanoscale — with a complete hardware-to-software stack verified by SPICE simulation and compiled microkernel binaries.