From Atom to
Operating System

Why Balanced Ternary?

Binary computing uses two states (0, 1). Balanced ternary uses three: −1, 0, +1. The key insight is that base-3 is the most efficient radix for information encoding — each digit carries log₂(3) ≈ 1.585 bits of information compared to 1 bit per binary digit.

Crucially, balanced ternary requires no two's complement representation. Negative numbers are represented naturally, and arithmetic operations on balanced ternary numbers are inherently symmetric around zero. Addition, subtraction, and comparison all become simpler.

At the physical level, a photonic-ternary device maps naturally to balanced ternary. A photon plus AC positive phase drives current in the positive direction (+1); no photon means no current (0); a photon plus AC negative phase drives current in the negative direction (−1). This is more natural than the binary trick of using voltage thresholds.

SWCNT@MWCNT Structure

The device is a metallic single-wall carbon nanotube (SWCNT) coaxially enclosed within a multi-wall carbon nanotube (MWCNT). Two concentric carbon tubes — that is the entire device. NEGF quantum transport simulation confirmed, room temperature operation.

• The SWCNT is a metallic ballistic conductor — the active conduction channel
• The MWCNT provides photonic gating and environmental shielding

Primary Embodiment — Contacted AC Device

Full embodiment details available under mutual NDA.

Trit Encoding

Trit encoding parameters — available under NDA.

Dual-Photon WDM Mode (Aspirational Embodiment)

In the aspirational contactless embodiment, a second drive photon is added alongside the gate photon, plus AC — yielding 12 distinguishable states from a single device. Wavelength-division multiplexing at the nanotube level. This contactless nanoantenna form represents the long-term roadmap.

• Device structureSWCNT@MWCNT (coaxial)
• SWCNT typeMetallic armchair
• Photonic gatingGate photon (MWCNT) — NDA
• WDM modeDrive photon (SWCNT) — NDA
• Electrical inputAC pulse polarity
• Trit encoding parametersAvailable under NDA
• SNRAvailable under NDA
• Simulation methodNEGF quantum transport
• Ballistic transportConfirmed, room temperature
• Dual-photon states12 per device (WDM)
• Max trit rate~500 GHz − 10 THz

The fabrication process grows coaxial SWCNT@MWCNT structures using chemical vapor deposition. Bulk carbon nanotubes are grown and the metallic SWCNT population is selected post-growth by Raman spectroscopy — a standard industry workflow. CNTs are abundant (~10⁹ per gram).

A notarized affidavit (Exhibit A) establishes that the core device concept was conceived in 2006, providing documentary evidence of priority.

Three-Device Cyclic Current-Mode SRAM

Conventional binary SRAM uses a 6-transistor bi-stable flip-flop. The PANINI processor introduces a three-device cyclic current-mode cell — a transistor-free topology where three cross-coupled THATTE devices form a cell with three stable states, not two. At 0.528 bits/device, this is 3.17× the storage density of a binary 6T SRAM.

Nodes N1 and N2 are cross-coupled through AC phase lines. The three stable configurations correspond to the three trit values, providing native ternary storage without requiring a binary-to-ternary encoding layer.

Modulo-3 Clock Generation

A ternary pipeline requires clock phases that divide time into three equal intervals. The PANINI processor implements a modulo-3 clock generator built from TMAJ3 gates and cyclic feedback, producing φ₀, φ₁, φ₂ phases used for three-stage pipeline control.

• SRAM cell typeThree-Device Cyclic Current-Mode (transistor-free)
• Storage density0.528 bits/device — 3.17× binary 6T
• Stable states per cell3 (−1, 0, +1)
• Cross-coupled nodesN1, N2 via AC phase lines
• Clock phasesφ₀, φ₁, φ₂ (modulo-3)
• Pipeline depth3-stage ternary
• Instruction setT3ISA (Thatte3)
• ALU operationsTernary ADD/MUL/TMIN/TMAX

The ManiT compiler is a full-stack compiler implemented in Rust (~26,800 LOC) with lexer, parser, semantic analysis, IR generation, and dual codegen backends. It targets both LLVM IR for binary host execution and T3ISA for native ternary hardware. A disassembler produces human-readable debug output (.t3d files).

The compiler and the microkernel described below are both public under AGPL-3.0 — see open source for the repositories, the emulator and the build instructions. Terms used on this page are collected in the glossary.

Compilation Pipeline

; ManiT Assembly — T3ISA Example
; Load trit constant +1 into register r0
TLOAD  r0, #[+1]

; Load trit constant −1 into register r1
TLOAD  r1, #[-1]

; Ternary ADD: r2 = r0 + r1 = 0
TADD   r2, r0, r1

; Conditional branch on zero
TBRZ   r2, .zero_case

; TMAJ3: majority of r0, r1, r2 → r3
TMAJ3  r3, r0, r1, r2

; Syscall: write trit to output
TSYS   0x01, r3

THATTE-OS is a compiled, running microkernel for balanced ternary hardware. Written in ManiT, compiled by the ManiT compiler to eleven .t3b binary modules, with full debug traces attached as patent appendices.

Privilege Domain System

The kernel implements three privilege domains — kernel (−1), supervisor (0), user (+1) — one per trit state. Privilege escalation and de-escalation are controlled by the 4-entry status register via dedicated TSYS/TRET instructions.

Kernel Modules

• boot.t3b — hardware init, memory map, jumps to init
• init.t3b — kernel entry, sets up stack, loads modules
• sched.t3b — modulo-3 round-robin process scheduler
• irq.t3b — interrupt vector table, IRQ dispatch
• proc.t3b — process creation, context switch
• syscall.t3b — T3ISA syscall interface layer
• mem.t3b — TritFS heap allocator integration
• io.t3b — ternary I/O port abstraction
• thatte_os.t3b — main kernel binary (all modules linked)

TritFS — Balanced Ternary Filesystem

TritFS addresses all storage resources using balanced ternary. A 5-trit address provides 3⁵ = 243 addressable locations. Memory heap blocks, file system inodes, and network buffers are all allocated using trit-arithmetic operations, eliminating the need for binary-to-ternary address conversion layers.

Appendix C of Thatte4 contains a complete 128-entry ASCII-to-balanced-ternary encoding table, enabling ternary-native text processing in THATTE-OS without binary translation.

TritTrie — Ternary Index Structure

A trie where each node has exactly three children, indexed by trit state (−1, 0, +1). Provides O(k) lookup, insert, and delete for trit-encoded keys of depth k. Used by TritFS for directory indexing and by the ManiT compiler for symbol tables.

Thatte7 — Three-Dimensional Array

Devices are arranged at the intersections of horizontal signal lines and vertical carbon-nanotube interconnects. Those vertical interconnects are dual-function: each one is part of the spatial addressing structure and simultaneously conducts heat from the interior of the array to a heat sink.

This matters because three-dimensional integration normally pays twice for density — once in routing, again in dedicated thermal structures — and heat is what stops conventional logic from stacking. Carbon nanotubes are exceptional axial thermal conductors, so the addressing path is already an excellent heat pipe. Devices are addressed without a per-device access transistor, removing the dominant area cost of a dense array.

Thatte8 — Contactless All-Photonic Device

A device variant with no electrical interface whatsoever. Three photonic inputs at distinct wavelengths replace every electrode, bonding pad, and wiring rail. Trit direction — the choice between +1 and −1, previously the job of an electrical AC terminal — is set by a piezoelectric shell driven optically.

Removing contacts removes contact resistance, electromigration, and the alignment and bonding steps that dominate fabrication difficulty at nanotube scale. A device with no electrical interface can also be placed anywhere light can reach, which is what makes dense three-dimensional integration practical.

Thatte9 — Binary-Ternary Bridge

Every new computing substrate faces the same adoption problem: it must coexist with what already exists. A ternary processor that cannot talk to a binary bus is a laboratory curiosity regardless of its physics. The bridge provides bidirectional translation between trit streams and conventional binary infrastructure.

Two encodings are disclosed. A fixed-width encoding maps each trit to two bits, leaving one bit pattern unused — repurposed as a hardware error flag, giving self-checking detection at no latency cost. A denser encoding utilizes the fact that five trits have 3⁵ = 243 states, which fits inside a single 256-state byte; the surplus values become a complete built-in framing and control protocol, so framing costs no bandwidth.

Thatte10 — Ternary Neural Processing Unit

Neural network weights drawn from {+1, 0, −1} are stored as ferroelectric polarisation states of a shell around each device and programmed optically, with no electrical weight-loading interconnect.

Multiplication by a ternary weight then requires no multiplier circuit at all. A weight of +1 routes the input trit through unchanged. A weight of −1 inverts it, which in balanced ternary is a wire crossing. A weight of 0 withholds the optical pulse entirely, leaving the device dark.

That last case is the significant one. On binary hardware a zero weight still costs a multiply and still burns energy, so sparsity has to be utilized by software. Here a zero weight is physically an absence of light — sparsity is structural, and saves energy whether or not anything schedules around it. Ternary quantisation is already where a great deal of inference is heading; this hardware runs it natively rather than emulating it.

Thatte11 — Error Correction over GF(3)

In balanced ternary, arithmetic over the finite field GF(3) is mostly not computation. Multiplication by 1 is a wire passing through. Multiplication by 2 — negation — is a wire crossing. Neither needs an active device. Addition is current superposition at a junction, following Kirchhoff's current law, followed by a threshold.

A GF(3) arithmetic network is therefore mostly interconnect, with active devices needed only at thresholds. On that substrate the patent builds ternary Hamming encode and decode, together with Reed–Solomon and LDPC constructions. Error correction is normally an area and power tax paid on every memory and every link, and most of that tax is spent on finite-field multipliers — exactly the part that is free here.

Thatte12 — Temperature-Modal Qutrit

The same double-walled structure operates in three regimes selected purely by temperature, with no structural modification. Warm, it is the classical photon-gated ternary switch of Thatte1. Cooled, phonon scattering falls away until the electron phase-coherence length exceeds the tube and quantum interference emerges. Colder still, the degenerate conducting channels of the inner nanotube provide the basis for a qutrit.

Quantum platforms are normally a separate technology from classical logic, with their own materials and fabrication, and the interface between them consumes enormous effort. Here there is no boundary to cross: one fabrication process yields both, and a three-level quantum unit is the natural match for balanced ternary logic, so the classical and quantum layers speak the same arithmetic.