T3ISA Explorer
Browse the balanced ternary instruction set architecture. Click a category to view its instructions, then click an instruction for encoding details.
Instruction Categories
Category
27-Trit Instruction Word
General Encoding Format
Each instruction is encoded in a fixed-width 27-trit word. The field layout above shows the general R-type format. Some instruction classes use alternate field arrangements (e.g., branch instructions may encode a wider address field). The 27-trit width equals 33 = one ternary "word" in the T3ISA convention.
Register File
General Purpose Registers
Special Registers
Status Register (SR) Fields
The status register encodes processor state using balanced ternary flags. Each field uses trit values −1, 0, +1 to represent three-valued conditions (e.g., PRIV: kernel / supervisor / user).
Why a Ternary Machine Needs Its Own Instruction Set
T3ISA is the instruction set architecture for PANINI, the balanced ternary processor in the THATTE stack. The obvious shortcut — take an existing binary ISA and re-encode it in trits — throws away most of what the hardware is for, because the operations a three-state machine performs cheaply are not the operations a two-state machine was designed around.
Comparison returns a trit, not a flag
A binary comparison produces one bit and therefore cannot distinguish “less” from “equal” from “greater” without a second test or a bank of condition flags. A balanced ternary comparison returns −1, 0 or +1 directly — the answer is the value. Three-way branches, sign extraction and clamping all collapse into single operations, and the status register above uses the same property: PRIV holds kernel, supervisor and user in one trit rather than encoding three states across two bits and leaving a fourth undefined.
Negation is wiring
Balanced ternary negates by flipping the sign of every trit, with no two's-complement carry and no asymmetric extreme value. So the ISA has no reason to provide separate add and subtract paths, and immediate constants cover a symmetric range: 12 trits of immediate field span ±265,720, centred exactly on zero.
The word is 27 trits because 27 is 3³
A fixed 27-trit instruction word carries roughly 42.8 bits of information (27 × log₂3), and the register fields are three trits each because three trits address exactly 27 registers. The powers line up all the way down, which is what keeps decoding cheap: no field straddles a boundary and no width is a compromise.
The compiler side of this is ManiT Compiler: Why Ternary Needs Its Own Instruction Set; the processor and ISA are covered by Thatte3, and the language, compiler and microkernel above them by Thatte6. To see the number system itself, the balanced ternary calculator shows conversion and carry propagation step by step.
Full Technical Brief Available Under NDA
Simulation data, quantum transport results, fabrication specifications, and complete patent claims are shared under mutual NDA only.
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