Between simulation-confirmed device physics and a working chip stand three fabrication problems that no current process solves simultaneously. Each section below maps the problem, the state of the field, and the available solutions.
CVD grows a chirality distribution. Only (8,8) armchair works. Addressed by Thatte1 metallocene CVD process (2006 priority).
Thatte1Diffraction (~355 nm) prevents per-device photon delivery at chip density. Reframed: separating addressing (electrical) from gating (optical).
Thatte2Gap variation, defect density, and axial misregistration all degrade trit margin. 54 dB SNR provides substantial tolerance; symmetry requires calibration.
Fabrication Thatte1The THATTE device inner conductor must be a metallic (8,8) armchair SWCNT. The (8,8) designation is not approximate: other armchair tubes ((7,7), (9,9)) have different diameters, different van der Waals coupling constants, and different conductance quantum values. Wrong chirality means wrong coupling — either too weak to gate or too strong to modulate.
Catalytic CVD nucleation is stochastic. Catalyst engineering narrows the distribution toward a family rather than a specific (n,m) pair. High single-chirality yield (>90%) has been demonstrated only at small scale (tens to hundreds of tubes) under highly controlled conditions.
| Method | Yield | Scale | Barrier |
|---|---|---|---|
| Unoptimised CVD | ~2–5% | Bulk | No selectivity |
| CoMo/Fe-Co CVD | ~15–30% | Bulk | Family only |
| Template / cloning | >90% | Tens of tubes | Not scalable |
| Gel chromatography | >99% | mg in solution | Destroys coaxial |
A unified metallocene CVD process grows (8,8)-enriched SWCNT directly inside an MWCNT channel in a single step, combining chirality selection with coaxial encapsulation. The metallocene precursor's molecular geometry biases nucleation toward armchair configurations while the MWCNT channel constrains the diameter range.
The specific catalyst formulation, temperature profile, and carbon source chemistry are the filed claims of Thatte1. The 2006 priority date predates published literature on in-situ encapsulation for armchair-selective growth.
Gel chromatography and density-gradient ultracentrifugation achieve >99% single-chirality purity, but both require disaggregation of the nanotube bundle into solution. This destroys the SWCNT@MWCNT coaxial geometry that is the whole point of the device. In-situ growth is the only route that achieves both chirality selectivity and coaxial encapsulation simultaneously.
The THATTE device is gated by a ~693 nm photon absorbed by the MWCNT outer wall. Photon absorption is the mechanism: it detunes MWCNT energy levels from the SWCNT, weakening inter-wall quantum coupling and raising conductance from 1.47 to 1.91 × G0. Without scalable photon delivery, there is no chip.
Two independent walls make free-space optical addressing infeasible at chip density:
| Approach | Confinement | BW | CNT status |
|---|---|---|---|
| Si photonic wire | ~250 nm | ~100 GHz | Single device |
| SiN waveguide | ~400 nm | ~50 GHz | Not published |
| Plasmonic slot | <50 nm | >1 THz | Research only |
| PhC nanobeam | ~100 nm | ~10 GHz | High Q, narrow BW |
Keep electrical contacts. Each device is individually addressable by its own electrical line — exactly what the semiconductor industry has mastered. Light provides a uniform gate-enable across the array. The per-device electrical line carries the logic; the photon is an enable signal, not a data carrier.
The diffraction problem disappears: light no longer needs to resolve individual devices. Density scales with electrical routing, not with optics. This is the primary embodiment in Thatte1 — the scalable path, and the honest answer to “but how does it scale?”
What it costs: The contactless story is gone. The photon becomes a clock, not a logic input. The 12-state WDM richness at the single-device level is sacrificed in favour of a fast ternary current-mode array. Smaller dream — but a real one, buildable this decade.
Each device sits on a SiN waveguide that carries its photon directly, coupling evanescently into the MWCNT wall. Per-device addressing comes for free: each waveguide is a private channel. Speed is excellent.
The catch: a SiN waveguide is ~450 nm wide, and neighbours must be several microns apart to prevent leakage. The device is 2 nm. Density crashes to millions of elements, not billions. Not the CPU — but a valuable fast photonic co-processor or interconnect fabric.
One shared waveguide carries many wavelengths; each device is tuned by its length to respond only to λN. Serves ~100 devices per bus (optical bandwidth + cavity Q limits). Tops out at hundreds of devices per bus, not millions.
Best used as a hybrid add-on to Option A: WDM bus feeding ~100-device clusters, electrical routing between clusters. Multiplies Option A rather than replacing it. Patent Thatte2 covers this architecture.
Near-field/plasmonic tricks squeeze light to 10–20 nm — still 10× too coarse for 2 nm device pitch. Holograms and spatial light modulators offer parallel illumination but remain diffraction-limited to ~350 nm spots. There is no known way to deliver an individually-chosen photon to each of a billion 2 nm devices at 2 nm spacing. This is not a failure of this project — it is a wall in physics as currently understood.
Electrons are born for dense individual addressing. Photons are born for fast contactless gating. Every version of this architecture that actually scales at chip density is a hybrid, and the simplest hybrid is Option A. The device was never meant to be an all-optical computer — the optical nature is a gift for speed and gate physics, not for routing. Let each medium do its own work.
Real fabrication produces a statistical ensemble. Every device differs from its neighbour in inter-wall gap, defect density, and coaxial alignment. The question is whether the device physics tolerates this spread.
| Source | Range | Effect on trit margin |
|---|---|---|
| Gap variation | ±0.03–0.05 nm | 5–20% ΔGmod |
| Defect density | 1 per 100–500 nm | G: 1.91 → toward 1.47×G0 |
| Axial offset | 0.05–0.2 nm | Trit ±1 asymmetry 3–5% |
Axial misregistration is the sharpest concern: off-axis coupling breaks I(+V) = −I(−V) symmetry and introduces a trit offset that the circuit layer must compensate per device.
The NEGF simulation result of SNR > 2000 (54 dB) is the central argument for disorder robustness. The trit margin is not set by a small voltage difference (as in DC CMOS) but by a photon absorption event with a near-binary outcome: absorbed or not. Even if defects halve the conductance modulation depth — from 0.44 G0 to 0.22 G0 — SNR remains above 1000, adequate for digital trit discrimination.
Gap variation changes coupling by ±10% for a ±0.05 nm departure from nominal (exp(−αΔd), α ≈ 2.1 nm−1). This is well within trit margin.
Growing the SWCNT inside the MWCNT in a single CVD step produces near-coaxial geometry from the start, without the axial offset risk of post-growth insertion. The Thatte1 fabrication process addresses misregistration at source rather than correcting it in the circuit.
Residual trit asymmetry (3–5% for 0.1 nm lateral offset) is detectable by the readout circuit. The Thatte2 gate library includes differential readout and a trit calibration offset register per device to compensate. This adds a one-time calibration step to the manufacturing flow but does not require process perfection.
Each problem has partial solutions in the literature. They remain hard because the solutions conflict:
| Solution for… | Conflicts with… | Mechanism |
|---|---|---|
| Chirality selectivity (slow, low-T CVD) | Disorder (defects) | Slow growth gives more time for structural rearrangement at the growth front → higher defect density |
| Defect reduction (high-T anneal) | Chirality yield | High-temperature annealing reshuffles tube chirality distribution |
| Post-growth chirality sorting | Disorder (coaxial geometry) | Sorting requires disaggregation; destroys SWCNT@MWCNT encapsulation |
| Planar substrate for photonic waveguide integration | Disorder (misregistration) | Planar substrate constrains MWCNT orientation and insertion geometry |
A unified fabrication process that solves all three constraints simultaneously is worth more — in engineering and patent terms — than three separate technique patents, because the coupling means the solutions must co-evolve. Patent Thatte1 is structured accordingly.
| Problem | Sub-problem | Patent | Coverage |
|---|---|---|---|
| Chirality yield | In-situ (8,8) growth during encapsulation | Thatte1 | Catalyst formulation and process conditions (filed, not disclosed) |
| Coaxial geometry preservation | Thatte1 | Unified single-step CVD (2006 priority date) | |
| Optical addressing | Electrical crossbar + global optical gate (primary) | Thatte1 | Primary embodiment; palladium contacts + AC bus + flood illumination |
| Per-device waveguide / evanescent coupling | Thatte2 | Photonic co-processor embodiment (filed) | |
| WDM multi-wavelength gate architecture | Thatte2 | Dual-photon mode, WDM-compatible gate library (filed) | |
| Disorder robustness | In-situ encapsulation for coaxial geometry | Thatte1 | Minimises axial misregistration at source |
| Differential readout + trit calibration | Thatte2 | Per-device trit offset correction in gate library |
International filings (PCT, USPTO, EPO, IPOS) are targeted for March 2027. Specific process parameters and circuit implementations are not disclosed publicly until that filing is secured. The coverage above reflects the scope filed with the Indian Patent Office (April 2026).
The narrative introduction: why the three problems are coupled and why they gate the simulation-to-chip transition.
The CVD science, the chirality problem, and the 2006 priority date for the fabrication patent.
The simulation that confirmed the device: ±74 µA trit currents, SNR > 2000, and the 54 dB headroom that disorder robustness depends on.
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