Fabrication · Manufacturing Research

The Three Hard Problems

Between NEGF-predicted device physics and a working chip stand three fabrication problems that no current process solves simultaneously. Each section below maps the problem, the state of the field, and the available solutions.

Blog Post CVD & Chirality Notes Patents

Problem 1

Priority approach filed

Chirality Yield

CVD grows a chirality distribution. Only the target metallic inner nanotube chirality works. Addressed by the Thatte1 chemical vapor deposition fabrication method (2006 priority).

Thatte1

Problem 2

Hybrid path

Optical Addressing at Scale

Diffraction (~355 nm) prevents per-device photon delivery at chip density. Reframed: separating addressing (electrical) from gating (optical).

Thatte2

Problem 3

SNR headroom

Disorder Robustness

Gap variation, defect density, and axial misregistration all degrade trit margin. Digital-grade signal-to-noise ratio provides substantial tolerance; symmetry requires calibration.

Fabrication Thatte1

Problem 1

Chirality Yield

The Problem

The THATTE device inner conductor must be a metallic armchair SWCNT of specific chirality. The chirality designation is not approximate: other armchair tubes have different diameters, different van der Waals coupling constants, and different conductance quantum values. Wrong chirality means wrong coupling — either too weak to gate or too strong to modulate.

Catalytic CVD nucleation is stochastic. Catalyst engineering narrows the distribution toward a family rather than a specific (n,m) pair. High single-chirality yield (>90%) has been demonstrated only at small scale (tens to hundreds of tubes) under highly controlled conditions.

Method	Yield	Scale	Barrier
Unoptimised CVD	~2–5%	Bulk	No selectivity
CoMo/Fe-Co CVD	~15–30%	Bulk	Family only
Template / cloning	>90%	Tens of tubes	Not scalable
Gel chromatography	>99%	mg in solution	Destroys coaxial

Open sub-problems

In-situ Raman verification of target chirality at wafer scale
Yield metric for coaxially encapsulated metallic SWCNT vs. isolated metallic SWCNT
Growth time vs. yield trade-off in chirality-selective CVD

Solution

Thatte1 — Primary approach

Chemical vapor deposition: in-situ chirality-selective encapsulation

A unified chemical vapor deposition fabrication method grows chirality-enriched SWCNT directly inside an MWCNT channel in a single step, combining chirality selection with coaxial encapsulation. The precursor chemistry and process geometry bias nucleation toward the target armchair configurations while the MWCNT channel constrains the diameter range.

The specific catalyst formulation, temperature profile, and carbon source chemistry are the filed claims of Thatte1. The 2006 priority date predates published literature on in-situ encapsulation for armchair-selective growth. Full fabrication specifications are available under mutual NDA.

Why post-growth sorting is not the answer

Sorting destroys coaxial geometry

Gel chromatography and density-gradient ultracentrifugation achieve >99% single-chirality purity, but both require disaggregation of the nanotube bundle into solution. This destroys the SWCNT@MWCNT coaxial geometry that is the whole point of the device. In-situ growth is the only route that achieves both chirality selectivity and coaxial encapsulation simultaneously.

Problem 2

Optical Addressing at Scale

The Problem

The THATTE device is gated by a photon. Optical gating is the mechanism and its details are specification-level detail, available under NDA. Without scalable photon delivery, there is no chip.

Two independent walls make free-space optical addressing infeasible at chip density:

Spatial: The Abbe diffraction limit is well above device pitch at 10¹⁰ density (10–50 nm). Free-space optics cannot address a single device.
Temporal: THATTE trit rate is 500 GHz–10 THz. Free-space modulators cap below 100 GHz commercially.

Approach	Confinement	BW	CNT status
Si photonic wire	~250 nm	~100 GHz	Single device
SiN waveguide	~400 nm	~50 GHz	Not published
Plasmonic slot	<50 nm	>1 THz	Research only
PhC nanobeam	~100 nm	~10 GHz	High Q, narrow BW

Open sub-problems

Evanescent coupling efficiency: SiN waveguide to MWCNT at the gate photon wavelength
Thermal crosstalk between adjacent waveguides and CNT devices
Electro-optic modulator bandwidth at 500 GHz–1 THz in CMOS platforms
WDM crosstalk at sub-nanometre channel spacing at chip scale

Solutions

Option A — Primary · Already filed

Electrical addressing + optical gate enable

Keep electrical contacts. Each device is individually addressable by its own electrical line — exactly what the semiconductor industry has mastered. Light provides a uniform gate-enable across the array. The per-device electrical line carries the logic; the photon is an enable signal, not a data carrier.

The diffraction problem disappears: light no longer needs to resolve individual devices. Density scales with electrical routing, not with optics. This is the primary embodiment in Thatte1 — the scalable path, and the honest answer to “but how does it scale?”

What it costs: The contactless story is gone. The photon becomes a clock, not a logic input. The 12-state WDM richness at the single-device level is sacrificed in favour of a fast ternary current-mode array. Smaller dream — but a real one, buildable this decade.

Option B — Photonic co-processor

Per-device waveguide + evanescent coupling

Each device sits on a SiN waveguide that carries its photon directly, coupling evanescently into the MWCNT wall. Per-device addressing comes for free: each waveguide is a private channel. Speed is excellent.

The catch: a SiN waveguide is ~450 nm wide, and neighbours must be several microns apart to prevent leakage. The device is 2 nm. Density crashes to millions of elements, not billions. Not the CPU — but a valuable fast photonic co-processor or interconnect fabric.

Option C — WDM cluster multiplier

One optical bus, each device tuned to its wavelength

One shared waveguide carries many wavelengths; each device is tuned by its length to respond only to λ_N. Serves ~100 devices per bus (optical bandwidth + cavity Q limits). Tops out at hundreds of devices per bus, not millions.

Best used as a hybrid add-on to Option A: WDM bus feeding ~100-device clusters, electrical routing between clusters. Multiplies Option A rather than replacing it. Patent Thatte2 covers this architecture.

The honest frontier — Unsolved by anyone

Near-field, plasmonic, and holographic schemes

Near-field/plasmonic tricks squeeze light to 10–20 nm — still 10× too coarse for 2 nm device pitch. Holograms and spatial light modulators offer parallel illumination but remain diffraction-limited to ~350 nm spots. There is no known way to deliver an individually-chosen photon to each of a billion 2 nm devices at 2 nm spacing. This is not a failure of this project — it is a wall in physics as currently understood.

The Reframe

Electrons are born for dense individual addressing. Photons are born for fast contactless gating. Every version of this architecture that actually scales at chip density is a hybrid, and the simplest hybrid is Option A. The device was never meant to be an all-optical computer — the optical nature is a gift for speed and gate physics, not for routing. Let each medium do its own work.

Problem 3

Disorder Robustness

The Problem

Real fabrication produces a statistical ensemble. Every device differs from its neighbour in wall spacing, defect density and coaxial alignment. The question is whether the device physics tolerates this spread.

Source	Range	Effect on trit margin
Gap variation	±0.03–0.05 nm	5–20% ΔG_mod
Defect density	1 per 100–500 nm	Reduces conductance modulation depth toward baseline
Axial offset	0.05–0.2 nm	Trit ±1 asymmetry 3–5%

Axial misregistration is the sharpest concern: off-axis coupling breaks I(+V) = −I(−V) symmetry and introduces a trit offset that the circuit layer must compensate per device.

Open sub-problems

NEGF simulation with gap disorder and defect disorder simultaneously
Statistical trit margin vs. process sigma model for a real CVD population
Circuit-level calibration for per-device trit offset at chip scale
Defect reduction by post-growth annealing without chirality redistribution

Solution

The SNR headroom argument

Digital-grade signal-to-noise ratio absorbs most disorder

The NEGF simulation confirms a digital-grade signal-to-noise ratio as the central argument for disorder robustness. The trit margin is not set by a small voltage difference (as in DC CMOS) but by a photon absorption event with a near-binary outcome: absorbed or not. Even if defects significantly reduce the conductance modulation depth, SNR remains adequate for digital trit discrimination.

Gap variation changes coupling within bounds well within trit margin. Full simulation parameters and disorder tolerance figures are available under mutual NDA.

Fabrication side — Thatte1

In-situ encapsulation minimises misregistration

Growing the SWCNT inside the MWCNT in a single CVD step produces near-coaxial geometry from the start, without the axial offset risk of post-growth insertion. The Thatte1 fabrication process addresses misregistration at source rather than correcting it in the circuit.

Circuit side — Thatte2

Differential readout + per-device calibration

Residual trit asymmetry (3–5% for 0.1 nm lateral offset) is detectable by the readout circuit. The Thatte2 gate library includes differential readout and a trit calibration offset register per device to compensate. This adds a one-time calibration step to the manufacturing flow but does not require process perfection.

Why They Cannot Be Solved Independently

The Coupling Problem

Each problem has partial solutions in the literature. They remain hard because the solutions conflict:

Solution for…	Conflicts with…	Mechanism
Chirality selectivity (slow, low-T CVD)	Disorder (defects)	Slow growth gives more time for structural rearrangement at the growth front → higher defect density
Defect reduction (high-T anneal)	Chirality yield	High-temperature annealing reshuffles tube chirality distribution
Post-growth chirality sorting	Disorder (coaxial geometry)	Sorting requires disaggregation; destroys SWCNT@MWCNT encapsulation
Planar substrate for photonic waveguide integration	Disorder (misregistration)	Planar substrate constrains MWCNT orientation and insertion geometry

A unified fabrication process that solves all three constraints simultaneously is worth more — in engineering and patent terms — than three separate technique patents, because the coupling means the solutions must co-evolve. Patent Thatte1 is structured accordingly.

Patent Coverage

What the THATTE Stack Addresses

Problem	Sub-problem	Patent	Coverage
Chirality yield	In-situ metallic inner nanotube growth during encapsulation	Thatte1	Catalyst formulation and process conditions (filed, not disclosed)
Chirality yield	Coaxial geometry preservation	Thatte1	Unified single-step chemical vapor deposition fabrication method (2006 priority date)
Optical addressing	Electrical crossbar + global optical gate (primary)	Thatte1	Primary embodiment; ohmic contacts + AC bus + flood optical coupling
	Per-device waveguide / evanescent coupling	Thatte2	Photonic co-processor embodiment (filed)
	WDM multi-wavelength gate architecture	Thatte2	Dual-photon mode, WDM-compatible gate library (filed)
Disorder robustness	In-situ encapsulation for coaxial geometry	Thatte1	Minimises axial misregistration at source
Disorder robustness	Differential readout + trit calibration	Thatte2	Per-device trit offset correction in gate library

Extended Coverage — Batch 2

Six specifications filed in August 2026 address two of these problems further, and add a tolerance path for residual defects that fabrication cannot eliminate.

Problem	Sub-problem	Patent	Coverage
Optical addressing	Eliminating electrical addressing entirely	Thatte8	Contactless all-photonic device — three wavelengths replace every electrode and wiring rail (filed)
Optical addressing	Addressing at array scale without per-device transistors	Thatte7	Spatial position combined with optical selection; vertical interconnects double as thermal paths (filed)
Disorder robustness	Tolerating residual defects rather than eliminating them	Thatte11	Error correction over GF(3), where field multiplication is wiring rather than active devices (filed)
Disorder robustness	Detecting corruption at the binary boundary	Thatte9	Spare code point in the bridge encoding as a hardware error flag — self-checking at no latency cost (filed)

Twelve complete specifications are now filed with the Indian Patent Office — Thatte1–6 on 9 April 2026 and Thatte7–12 on 8 August 2026. International filings follow those priority dates. Specific process parameters and circuit implementations are not disclosed publicly.