The Three Hard Problems:
Chirality Yield, Optical Addressing at Scale,
and Disorder Robustness

Why These Three?

The THATTE device has a deceptively simple structure: one metallic (8,8) armchair single-wall carbon nanotube (SWCNT) coaxially inside a multi-wall carbon nanotube (MWCNT), separated by a 0.34 nm van der Waals gap. A photon at ~693 nm gates the device; an AC voltage determines trit polarity. NEGF simulation confirms ±74 µA trit currents at 0.5 V and SNR > 2000.

None of that physics is in doubt. The hard part is making it in quantity. When you ask what fabrication obstacles must be cleared to go from one lab-grade device to a chip with billions of such switches, three problems dominate every other concern:

These are not peripheral engineering details. Each one, if unsolved, prevents the device from functioning at all. Understanding them precisely is the first step toward solving them — and toward knowing which parts of the solution are already covered by patent.

Problem 1: Chirality Yield

A carbon nanotube's chirality — the (n,m) integers that describe how the graphene sheet is rolled up — determines its electronic character completely. The THATTE device requires a metallic (8,8) armchair SWCNT as its inner conductor. Armchair tubes satisfy n = m, which guarantees metallicity regardless of diameter. The (8,8) tube specifically has a diameter of ~1.08 nm, a ballistic conductance of 2G₀, and the right van der Waals coupling geometry for the 0.34 nm gap inside a standard MWCNT.

The problem is that catalytic CVD growth does not produce a single chirality. A typical synthesis yields a statistical distribution: roughly one-third metallic tubes (including armchair and some near-armchair types), two-thirds semiconducting, and within the metallic fraction, dozens of distinct (n,m) pairs. Even optimised catalyst engineering — bimetallic particles, narrow size distributions, temperature ramping — moves the distribution rather than selecting a single point within it.

The cloning approach — using a short segment of the desired chirality as a seed for continued growth — is the most promising route to high selectivity, but it currently operates at the level of individual tubes in controlled experiments, not at wafer scale. Post-growth sorting by gel chromatography or density-gradient ultracentrifugation achieves excellent purity but destroys the SWCNT@MWCNT coaxial geometry that is the whole point of the THATTE device.

The implication is stark: to get a device, you need to either grow (8,8) selectively in situ inside an MWCNT channel, or grow and sort before assembly, then re-encapsulate — a process that introduces contamination and misalignment at every step.

Patent Thatte1 (fabrication method) addresses this through a unified metallocene CVD process. The specific catalyst formulation, temperature profile, and precursor chemistry are the core of the filed claims and are not disclosed here. The 2006 priority date on the fabrication concept is the key anchor; see the CVD and Chirality Control post for the priority evidence discussion.

Crucially, post-growth sorting is not a substitute. Gel chromatography and density-gradient ultracentrifugation achieve >99% single-chirality purity, but both require disaggregating the nanotube bundle into solution — which destroys the SWCNT@MWCNT coaxial geometry that is the whole point of the device. In-situ growth is the only route that achieves chirality selectivity and coaxial encapsulation simultaneously.

Problem 2: Optical Addressing at Scale

The THATTE device is photon-gated. A photon at ~693 nm absorbed by the MWCNT wall detunes its energy levels from the inner SWCNT, weakening inter-wall quantum coupling and allowing the SWCNT conductance to rise from 1.47 to 1.91 × G₀. That optical gating event is what distinguishes trit 0 from trit +1 or −1.

At the level of a single device in a scanning microscope setup, delivering a photon is straightforward: focus a laser, wait for absorption. At chip scale, the problem becomes severe in two independent ways.

The density problem. A chip with 10¹⁰ THATTE devices would have a device pitch on the order of 10–50 nm. The diffraction limit of a 693 nm photon in free space is ~347 nm — an order of magnitude larger than the device pitch. Free-space optics cannot address individual devices at this density. Any solution must use near-field coupling, sub-wavelength confinement, or integrated photonics to route light to each device.

The speed problem. The THATTE device can switch at trit rates of ~500 GHz to 10 THz (hot-carrier relaxation limit). For the photon gate to keep up, the optical signal must also be modulated at those frequencies. Free-space laser modulation at terahertz rates exists only in laboratory settings.

The most tractable near-term path for per-device photonic delivery is integrated silicon nitride waveguides fabricated on the nanotube substrate, coupling light evanescently into the MWCNT wall. This has been demonstrated for individual CNT devices but not at chip density. But there is a more direct answer, and it is worth working through all four paths honestly.

Four Paths Through the Addressing Problem

Option A: Stop insisting light must address. Keep the electrical contacts. Each device is individually addressable by its own electrical line — exactly what the semiconductor industry has spent seventy years mastering at billions of devices. Light provides a uniform gate-enable over the array. The per-device electrical line carries the logic; the photon is an enable signal, a clock almost — not a data carrier to a specific device.

The moment you write that down, the hard problem vanishes. The diffraction limit was a self-inflicted wound: there is no requirement that light carry the address. Electrons are simply better at dense individual addressing, and photons are better at fast uniform gating. Let each do its own work.

This is not a retreat from the original design — it is the primary embodiment filed in Thatte1. What it costs: the all-optical contactless story is gone, and the photon gives up its role as a 12-state WDM logic input at the single-device level. The result is a fast ternary current-mode array, not the full photonic jewel. Smaller dream. But a real one, buildable this decade, standing on electrical addressing infrastructure the industry has already solved.

Option B: Give each device its own waveguide. A SiN waveguide runs to each device and couples evanescently into the MWCNT wall. Per-device addressing comes for free: each waveguide is a private channel. Speed is excellent. Demonstrated in principle (Pyatkov et al., 2016; He et al., 2018) for individual devices.

The catch is density. A SiN waveguide is ~450 nm wide; neighbours need a few microns clearance to prevent leakage. The device is 2 nm. The waveguide that feeds it is a thousand times larger. You have built the world’s smallest switch and marooned it in an ocean of optical plumbing. Density crashes to millions of elements, not billions. Not the main CPU — but a viable, valuable fast photonic co-processor or interconnect for high-value work.

Option C: One shared bus, each device tuned to its wavelength. A single waveguide carries many wavelengths; each device is tuned by its nanotube length to respond only to λ_N. Telecom routinely runs 80–160 WDM channels on one fibre. Address device N by sending λ_N down the shared guide.

The romance cools when you count. The usable optical window holds only a few hundred distinguishable channels, and cavity Q of 100–1000 makes each device’s response several nanometres broad — so channels must be spaced far apart to avoid crosstalk. Realistically: tens to at most a couple hundred devices per bus, not millions. And tube length now must be atomically controlled, because length sets the resonance wavelength. The hardest fabrication problem just got harder.

Option C is not a standalone solution, but it is useful as a multiplier bolted onto Option A: WDM bus feeding ~100-device clusters, electrical routing between clusters. A rich seam of dependent claims in Thatte2, and a credible medium-term roadmap.

The honest frontier. Near-field and plasmonic approaches squeeze light confinement to 10–20 nm — real physics, demonstrated in the lab — but 2 nm device pitch is still an order of magnitude beyond them. Holographic and spatial-light-modulator approaches offer parallel free-space illumination (used in optical neural networks and cold-atom arrays) but remain diffraction-limited to ~350 nm spots. There is no known way, by anyone, to deliver an individually-chosen photon to each of a billion 2 nm devices at 2 nm spacing. This is not a failure of this project. It is a wall in physics as currently understood.

Electrons address. Photons gate. The architecture is hybrid by design, not by compromise. Every version of this that actually scales is a hybrid, and the simplest hybrid is Option A — which is already what was filed. The all-optical computer was never the claim; the claim is a fast ternary switch with photonic gating. Those are different things, and the second one scales.

Problem 3: Disorder Robustness

Even if chirality yield is solved and photons are delivered precisely, every fabricated THATTE device will differ from its neighbours. No CVD process produces perfectly identical nanotubes. The question is not whether disorder exists — it always does — but whether the device physics tolerates the amount that real fabrication introduces.

There are three principal sources of disorder in the SWCNT@MWCNT system:

• Van der Waals gap variation. The nominal inter-wall gap is 0.34 nm. In practice, local curvature, encapsulation method, and thermal annealing can cause gap variations of ±0.03–0.05 nm. Since the inter-wall quantum coupling (which is the gating mechanism) depends exponentially on this gap, small variations translate to large changes in the conductance modulation depth — and therefore trit margin.
• Defect density. CVD-grown nanotubes contain sp³ defects, vacancies, and Stone-Wales rearrangements at densities that depend on growth conditions. Each defect is a backscattering site that reduces mean free path and converts ballistic to diffusive transport. The NEGF simulation result of 1.91 × G₀ assumes near-ideal ballistic transport; real defect densities in as-grown material (typically 1 defect per 100–500 nm) will reduce this figure.
• Geometric misregistration. The SWCNT must sit coaxially inside the MWCNT. Off-axis displacement, even by a fraction of a nanometre, breaks the cylindrical symmetry of the coupling and introduces position-dependent variation in device response. Assembly methods that rely on in-situ encapsulation are more coaxial than post-growth insertion, but neither is perfect.

The THATTE device's SNR of > 2000 (54 dB) provides substantial headroom. A factor-of-two reduction in conductance modulation depth due to defects would still leave SNR in the hundreds — far above the minimum needed for reliable trit discrimination. This is one of the structural advantages of the photonic-AC paradigm over DC gate-controlled devices: the trit margin is set by a high-SNR optical event (photon absorption or not), not by a small voltage difference.

Geometric misregistration is more concerning for the symmetry requirement: the NEGF simulation shows I(+V) = −I(−V) (perfect trit ±1 symmetry) only for a coaxial geometry. Off-axis coupling breaks this symmetry and introduces a trit offset that the circuit layer must compensate. This is a solvable problem at the circuit level (differential readout, calibration), but it adds design overhead.

Patent Thatte1 addresses disorder robustness through the fabrication method itself: a process that produces near-coaxial geometry from the start is more robust than one requiring post-assembly alignment. The filed claims cover the specific in-situ encapsulation approach.

Why All Three Are Hard at the Same Time

Each problem individually has partial solutions in the literature. The reason these remain "the three hard problems" is that the solutions conflict.

High chirality selectivity favours slow, low-temperature CVD with narrow catalyst size distributions — conditions that also increase defect density because slower growth gives more time for structural rearrangements at the growth front. Reducing defects favours high-temperature annealing, which randomises the chirality distribution. Integrated photonic waveguides for optical addressing require a planar substrate geometry that constrains the MWCNT orientation, adding misregistration risk. Post-growth sorting for chirality purity destroys the coaxial geometry that disorder robustness depends on.

You cannot fix chirality, then fix optics, then fix disorder as three independent sub-problems. They are coupled through the fabrication process. The solution must address all three simultaneously in a single process architecture.

This coupling is precisely why a unified fabrication patent — one that addresses all three constraints within a single process flow — is more valuable than three separate technique patents. Patent Thatte1 is structured as a unified process for exactly this reason.

What the THATTE Architecture Does About It

The THATTE patents address each problem at its appropriate layer:

• Chirality yield (Thatte1): The metallocene CVD fabrication method targets (8,8) armchair selection through catalyst engineering and growth conditions documented with a 2006 priority date.
• Optical addressing (Thatte1 + Thatte2): The primary solution is electrical addressing with optical gate-enable — already the primary embodiment in Thatte1. This makes the diffraction wall irrelevant by design. Thatte2 additionally covers per-device evanescent waveguide coupling (photonic co-processor path) and WDM cluster architecture as hybrid extensions.
• Disorder robustness (Thatte1 + Thatte2): The fabrication method provides in-situ coaxial encapsulation to minimise misregistration; the gate library includes differential readout and trit calibration to handle residual device-to-device variation.

The deeper reference page — The Three Hard Problems — covers the current literature state, open sub-problems, and the specific patent claim mapping in more detail.