Balanced Ternary Error Correction over GF(3)

Overview

Error-correcting circuits built directly on balanced ternary arithmetic over the finite field GF(3). The structural observation is that in balanced ternary, the field's multiplications are not computations at all. Multiplication by 1 is a wire passing through. Multiplication by 2 — which in balanced ternary is negation — is a wire crossing. Neither requires an active device.

Addition is performed by current superposition at a junction, following Kirchhoff's current law, followed by a threshold operation. The result is that a GF(3) arithmetic network is mostly interconnect, with active devices needed only at the thresholds.

On this substrate the patent builds a ternary Hamming encoder and decoder, together with Reed–Solomon and LDPC constructions over GF(3). Parity-check matrices, code parameters, and component counts are shared under mutual NDA.

Key Innovations

• GF(3) multiplication implemented as wiring rather than active devices
• Negation as a wire crossing — zero-device sign inversion
• Addition by Kirchhoff current superposition followed by thresholding
• Ternary Hamming encoder and decoder circuits
• Reed–Solomon and LDPC constructions over GF(3)
• Substantially fewer active components than binary error-correction equivalents

Why It Matters

Error correction is normally an area and power tax paid on every memory and every link. Most of that tax is spent on finite-field multipliers.

Balanced ternary makes the field small enough that its multiplication table is trivial, and signed enough that negation is free. The arithmetic that costs the most in binary is the arithmetic that costs nothing here.

Disclosure

This page describes the architecture and purpose of the invention. Specific parameters — dimensions, thresholds, wavelengths, code assignments, and simulation figures — together with the complete claim set are shared under mutual NDA. Contact manish@manitlab.org to request access.

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