SPICE Verification: Proving the
Ternary Gate Library Works

Why Simulate Before Fabricating?

Fabricating a carbon nanotube FET device is expensive, time-consuming, and requires cleanroom access. SPICE simulation using an established device model lets us verify that the circuit design is correct before committing to fabrication — and, critically for the patent process, provides reproducible, third-party-verifiable proof of operation.

For the THATTE gate library (Thatte2), we needed to verify three claims:

1. The ternary inverter (TINV) switches symmetrically at the design threshold voltage
2. The TINV has equal current drive in positive and negative directions (balanced ternary requires symmetry)
3. The ternary majority gate (TMAJ3) correctly implements median(A, B, C) for all 27 input combinations

All three were verified. Here is how.

The Simulation Setup

Platform

All simulations were run on Debian 13, AMD EPYC 9334 (64-core), with dual AMD Radeon Pro W7900 GPUs (unused for simulation — ngspice is CPU-bound). The choice of hardware does not affect numerical results; any modern platform running ngspice-44.2 will reproduce these results exactly.

The CNFET Model

The Stanford University CNFET SPICE model, published by Deng and Wong in IEEE Transactions on Electron Devices (2007), is the most widely-used compact model for carbon nanotube FET simulation. It models ballistic transport in single-wall CNTs with parameterised chirality and diameter, and has been validated against experimental device data from multiple research groups.

The model file (CNFET_Stanford.sp) is shared across all patent simulations from a common directory, ensuring consistency. Key parameters used:

TINV: The Ternary Inverter

Circuit Description

The TINV consists of two complementary THATTE devices in series:

• A P-type CNFET (threshold voltage +0.3 V) connected from VDD to output
• An N-type CNFET (threshold voltage −0.3 V) connected from output to VSS

When input = +1 (V_in = +1 V): the P-type turns off, N-type turns on strongly, output pulled to VSS (−1 V) → output trit = −1.

When input = 0 (V_in = 0 V): both devices are at threshold, output floats to mid-rail (0 V) → output trit = 0.

When input = −1 (V_in = −1 V): the P-type turns on strongly, N-type turns off, output pulled to VDD (+1 V) → output trit = +1.

V_th Symmetry Result

We swept V_in from −1 V to +1 V and measured the output voltage. The inverter transition occurs symmetrically in both directions, confirming the threshold symmetry requirement for balanced ternary operation. Exact threshold values are available under NDA.

ngspice-44.2: TINV DC Sweep Results
  V(in) = −1.000 V → V(out) = +1.000 V (trit +1)  ✓
  V(in) = −0.300 V → Transition point (−1 → 0)     ✓
  V(in) =  0.000 V → V(out) =  0.000 V (trit  0)  ✓
  V(in) = +0.300 V → Transition point ( 0 → +1)    ✓
  V(in) = +1.000 V → V(out) = −1.000 V (trit −1)  ✓

  V_th symmetry: symmetric ±V_th  →  TARGET MET

Current Symmetry Result

This is the most critical verification for balanced ternary. If the current at the output when input = −1 (drive to +1) is not equal in magnitude to the current when input = +1 (drive to −1), the gate has an asymmetric drive strength that would cause timing and voltage margin problems in a real circuit.

The requirement we set: |I(−1) / I(+1)| ≥ 0.95 (5% tolerance). The result:

The ratio of exactly 1.0000 is not a coincidence — it reflects the symmetric geometry of the complementary CNFET pair and the precisely balanced threshold voltages. This is what balanced ternary requires, and the device delivers it.

The leakage at V_in = 0 V (both devices in the off/near-off state) is acceptably low for a research platform — it represents the sum of sub-threshold leakage from both the P-type and N-type devices, and is well below the switching current by five orders of magnitude. Exact figures are available under NDA.

TMAJ3: The Ternary Majority Gate

Why Majority Matters

In binary logic, the fundamental universal gate is NAND (or NOR). In balanced ternary, the analogous role is played by the ternary majority function: median(A, B, C) — the value that appears at least twice, or the middle value when sorted.

TMAJ3 is not just academically interesting — it is the basis of the PANINI processor's ALU. Ternary adder carry logic, majority voting in fault-tolerant systems, and median filtering (common in signal processing) all use TMAJ3 directly.

The 27-Entry Truth Table

With three inputs each taking three values, there are 3³ = 27 possible input combinations. We simulated all 27 using a parameterised sweep and compared the output to the expected median(A, B, C).

All 27 entries match. Here is a representative subset:

The output voltages are exact rail voltages — +1.000 V, 0.000 V, −1.000 V — with no intermediate states, confirming full ternary saturation. This is the correct behaviour for a combinational gate in a ternary logic family.

TMIN2 and TMAX3: Quick Results

The two remaining cells — TMIN2 (ternary minimum of two) and TMAX3 (ternary maximum of three) — were verified with smaller truth tables (9 entries and 27 entries respectively):

TMIN2 Verification: 9/9 entries correct
  min(−1, −1) = −1 ✓    min(−1, 0) = −1 ✓    min(−1, +1) = −1 ✓
  min(0, −1)  = −1 ✓    min(0, 0)  =  0 ✓    min(0, +1)  =  0 ✓
  min(+1, −1) = −1 ✓    min(+1, 0) =  0 ✓    min(+1, +1) = +1 ✓

TMAX3 Verification: 27/27 entries correct
  max(−1, −1, −1) = −1 ✓  ... max(+1, +1, +1) = +1 ✓
  All entries verified. PASS.

What These Results Mean for Fabrication

SPICE results using a calibrated compact model are the standard pre-fabrication verification step in IC design. The results here establish several things:

• The device model supports balanced ternary operation. The Stanford CNFET model, when parameterised for the target threshold and three-rail supply, produces stable, symmetric three-state behaviour. SPICE verification is complete and results confirm trit switching. This validates the physical basis of the design.
• The gate library design is correct. TINV, TMIN2, TMAX3, and TMAJ3 all produce correct outputs for all input combinations. A layout-level simulation (post-layout SPICE with parasitics) would be the next step.
• The CNFET parameters are achievable. The selected CNT chirality with HfO₂ gate dielectric represents a device grounded in published research. The simulation parameters are based on real materials. Specific parameters are available under NDA.

The next verification steps before tape-out would be:

1. Schematic-level simulation of multi-gate circuits (adder, comparator)
2. Layout-level simulation with extracted parasitics (post-layout SPICE)
3. Monte Carlo variation analysis (threshold voltage, tube diameter distribution)
4. Temperature corner simulations (−40 °C, +85 °C, +125 °C)

These are standard VLSI sign-off steps. The THATTE gate library has passed the first and most fundamental test: the physics works.