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Most computing research advances a single layer: a new transistor material, a new cache architecture, a new scheduling algorithm. The THATTE stack is different. It is a complete, vertically integrated computing architecture — from the quantum physics of a two-nanotube switch, through logic gates, processor, memory, security, all the way to a compiled, running operating system.
Everything is designed around one central choice: balanced ternary. Not binary with a twist. Not multi-level cell storage that approximates analog. True three-valued logic, where the three states are −1, 0, and +1 — symmetric, signed, and physically natural in the device that implements them.
This post is the map. It explains each layer, how they connect, and why the whole is more than the sum of its parts.
Why Ternary? The Mathematical Case
Binary is not the optimal radix for information storage. This has been known since before transistors existed. The most information-efficient integer base — the one that minimises the number of digit positions needed for a given range of values — is e ≈ 2.718. Since we must use whole numbers, the closest integer is 3.
Each trit (ternary digit) carries log₂(3) ≈ 1.585 bits of information. A binary digit carries exactly 1 bit. For the same word length, a ternary word encodes 58.5% more information than a binary word. That is not a small margin — it is the difference between a 32-trit word and a 51-bit word.
The “balanced” in balanced ternary refers to the choice of digit set: {−1, 0, +1} rather than {0, 1, 2}. Centring the range on zero has consequences that reach through every layer of the system.
| Property | Binary | Balanced Ternary |
|---|---|---|
| Digits per number | n bits | n/1.585 trits (fewer) |
| Negative numbers | Two’s complement convention | Flip all signs — no convention |
| Symmetric range | No (−2ⁿ⁻¹ to +2ⁿ⁻¹−1) | Yes (−N to +N exactly) |
| Rounding | Requires convention (round-half-even) | Natural — truncate to nearest |
| Comparison sign | Sign-bit inspection (signed) or trivial (unsigned) | Most significant non-zero trit |
Balanced ternary eliminates two’s complement entirely. Negation is trivial: flip the sign of every trit. There is no overflow asymmetry, no “minimum integer” edge case, no sign extension on right shift. Arithmetic units are simpler. Comparators are symmetric. Every operation that binary handles as a special case, balanced ternary handles naturally.
This was proven in practice, not just theory. In 1958, Nikolay Brusentsov at Moscow State University built the Setun — the world’s first and only balanced ternary computer. It ran until 1965. Its arithmetic unit was genuinely simpler than contemporary binary machines. The Setun was discontinued not because ternary failed, but because binary had already won the market and components were unavailable. Network effects, not physics, killed ternary computing in the 1960s.
The THATTE stack is the attempt to finish what the Setun started — at the nanoscale, with photonics, and with a complete verified system.
Why Now? The Physical Case
Binary computing is approaching fundamental limits. At sub-5 nm gate lengths, quantum tunnelling, thermal noise, and fabrication variability make further scaling extraordinarily difficult. The CMOS roadmap is not running out of ideas; it is running out of physics.
Carbon nanotube field-effect transistors (CNFETs) are one of the most mature post-silicon transistor candidates. IBM demonstrated a CNFET ring oscillator at sub-10 nm pitch. Stanford built a 16-bit CNFET processor. TSMC has active CNFET research programmes. The material science obstacles are real, but the field is closing in on fabrication readiness.
CNFETs are also, physically, natural ternary devices. In a metallic armchair carbon nanotube, current flows ballistically — like a waveguide, not a resistor. That current is not limited to “on” or “off.” AC signals propagate through the tube and emerge with the polarity of the driving signal intact. Positive phase: positive current. Negative phase: negative current. No signal: zero current. Three states, three physical conditions, zero ambiguity.
The right moment to define the ternary paradigm for CNFET computing is before that technology matures — not after. That is why the THATTE filings happened in 2026.
The Device: Two Carbon Nanotubes
The THATTE device is structurally simple: a single-walled carbon nanotube (SWCNT) inside a multi-walled carbon nanotube (MWCNT). Two concentric tubes separated by a 0.34 nm van der Waals gap. That is the entire device.
The switching mechanism is photonic. The MWCNT normally suppresses the SWCNT’s conductance through inter-wall quantum coupling. When a photon at the right wavelength is absorbed by the MWCNT, its energy levels shift, the coupling weakens, and the SWCNT’s conductance rises. The AC voltage applied to the terminals then determines the direction of current — which encodes the trit.
The key numbers, from NEGF quantum transport simulation:
- Trit +1 current: +74 µA at 0.5 V
- Trit −1 current: −74 µA at 0.5 V (perfect symmetry)
- Trit 0 noise floor: ~35 nA (well below threshold)
- Signal-to-noise ratio: > 2000 (54 dB)
- Current symmetry I(+V) / |I(−V)|: 1.000 within simulation precision
An SNR of 54 dB is not marginal. It is louder relative to the noise floor than most RF communication links. The device is not “probably digital” — it is digital, by a large margin. The three states are unambiguous.
Crucially, trit 0 is not a gate-controlled “off” state. The SWCNT is always ready to conduct. Trit 0 is the absence of input: no photon, no AC signal. This is a transmission line, not a switch. The distinction matters at every layer above it.
The Six Layers
Six patents cover the complete stack, filed as complete specifications with the Indian Patent Office on 9 April 2026. Each patent is a self-contained invention that also depends on the layers below it. Together they form a single coherent system.
Device Fabrication and Switching
The SWCNT@MWCNT photonic-ternary transducer: structure, fabrication via metallocene CVD, post-growth chirality selection, photonic switching mechanism, and the proof that three trit states are physically stable and distinguishable. This is the physical foundation. Every layer above it implements on top of what this layer proves.
Ternary Gate Library and Arithmetic Architecture
Ternary logic is not binary logic with a third state bolted on. The gate library is designed from first principles: TMIN, TMAX, TNOT (which is just sign inversion), consensus functions, and the arithmetic building blocks — ternary half-adder, full-adder, carry-save multiplier. Balanced ternary arithmetic is structurally simpler than binary arithmetic because the number system handles sign natively. 23 claims across 18 figures.
Photon-Clocked Balanced Ternary Processor
A processor architecture designed for balanced ternary from the register file up. The clock is optical — photon pulses drive instruction execution, not a crystal oscillator. The instruction set (T3ISA) has no sign bit, no two’s complement, no unsigned/signed distinction. Every register, every ALU operation, every branch condition is naturally signed. 21 claims, 10 figures.
Memory, Interconnect, and Associative Lookup
Memory fabric management, ternary bus protocols, and the trit-trie — a tree-structured associative lookup optimised for balanced ternary addresses. When your address space has three children per node instead of two, standard binary data structures are not just suboptimal; they are wrong. Thatte4 defines the right data structures for a ternary address space, along with the interconnect protocols that move trits between processor, memory, and peripherals. 29 claims, 8 figures.
Cryptographic Primitives and Design-for-Test
Security hardware in balanced ternary. Ternary cryptographic primitives differ from binary counterparts because the key space is naturally larger and signing is structural rather than conventional. Design-for-test (DFT) and built-in self-test (BIST) infrastructure adapted for ternary logic — testing a three-valued circuit requires test patterns that binary test tools do not generate. 31 claims across 14 figures, the most claims in the stack.
Programming Language, Compiler, Operating System, and Emulator
ManiT is a statically typed, balanced ternary programming language. The ManiT
compiler (Rust, ~11,600 lines of code) targets both LLVM IR for host execution
and T3ISA binary for ternary hardware. THATTEOS is a microkernel written
entirely in ManiT — interrupt handling, privilege domains, virtual memory,
message-passing IPC, scheduler — compiled to 72 KB of
.t3b ternary binaries that run in the T3ISA emulator.
The cycle-accurate emulator is also patented.
22 claims, 8 figures.
What Has Been Built and Verified
The six patents are not design documents. Each layer was implemented and verified before filing. This matters because patents covering unverified designs are speculation; patents covering verified implementations are a different category of claim entirely.
| Layer | Verification Method | Key Result |
|---|---|---|
| Thatte1 (Device) | NEGF quantum transport (Kwant) | ±74 µA, SNR > 2000 |
| Thatte1 (Optical) | GW+BSE many-body perturbation (Yambo) | M11 exciton at 693 nm (2.4% from claim) |
| Thatte1 (Material) | DFT + DFPT (Quantum ESPRESSO, GPAW) | HfZrO₂ ferroelectric confirmed |
| Thatte2 (Logic) | SPICE / NEGF-parameterised simulation | Full gate library verified |
| Thatte3–5 (Hardware) | T3ISA emulator (cycle-accurate) | Instruction execution confirmed |
| Thatte6 (Software) | ManiT compiler + T3ISA emulator | THATTEOS boots and runs |
The device physics was verified by three independent simulation methods: NEGF quantum transport for electrical characteristics, GW+BSE many-body perturbation theory for optical absorption, and DFT with DFPT for phonon and ferroelectric properties of the memory material. These are not toy models — they are the same methods used in peer-reviewed computational materials science.
The software stack was verified end-to-end: ManiT source code was compiled to T3ISA binary by the Rust compiler, and that binary was executed in the cycle-accurate T3ISA emulator. THATTEOS boots. System calls work. The scheduler runs. This is not a prototype language or a design sketch; it is a working system.
What Makes This Different
Balanced ternary has been proposed many times. What is almost always missing is the complete vertical stack — a single coherent architecture where every layer was designed knowing the properties of the layers above and below it.
Consider what it means that the SWCNT is a metallic armchair tube, not a semiconducting one. A metallic SWCNT is a ballistic conductor. Current in = current out, with direction and magnitude preserved. This is a transmission line, not a resistive switch. AC signals propagate through it with their polarity intact. When you build a gate library on top of that, the gate design choices reflect this property. When you build an ISA on top of those gates, the instruction encoding reflects the gate properties. When you write an operating system in a language designed for that ISA, the OS’s memory model reflects the address space structure.
Each layer in the THATTE stack was designed knowing what it was sitting on top of and what would run on top of it. That vertical coherence is rare — most architectures accumulate layers over decades, with each layer inheriting the assumptions of the layer below it rather than reasoning from first principles about what the layer below actually is.
The THATTE stack starts from a 2 nm quantum device and reasons upward. Every design decision at the OS level is traceable, in principle, to a property of the physics of the SWCNT@MWCNT device.
The 2006 Thread
The core concept — a three-state carbon nanotube device that encodes trits through current direction rather than current magnitude — was first conceived in 2006. At that time, the CNFET field was in its early years, and balanced ternary computing was not on any mainstream research agenda.
Twenty years elapsed between that original insight and the complete specification filings in April 2026. Those two decades were not idle. The CNT synthesis technology matured. Computational tools (NEGF, GW+BSE, DFPT) reached the fidelity needed to verify device physics without a fabricated sample. The programming language and compiler were built. The operating system was written and compiled.
The Setun was built in 1958 and ran for seven years before being discontinued. It proved balanced ternary works. The THATTE stack proves it works at the nanoscale, with photonics, with a complete verified system — and with international patent protection for the inventor.
What Comes Next
International filings (PCT and direct national phase) are the immediate priority. The Indian complete specifications establish the filing date; PCT coverage extends that date globally.
On the simulation side, the Fe-catalyst LAMMPS ReaxFF molecular dynamics study of CNT CVD growth is ongoing — understanding how (8,8) armchair tubes form under iron catalyst conditions. If the simulation confirms a viable synthesis pathway, that becomes a seventh patent (Thatte7, fabrication methods).
On the software side, the ManiT compiler and THATTEOS kernel are targeted for public release — after international filings are secured. The hardware patents (Thatte1–Thatte5) protect the physical inventions. The software (Thatte6) will be released freely when the protection is in place. The intent was always to protect first, then make the knowledge available to anyone who wants to build on it.