THATTE-OS: Building a Microkernel
for Ternary Hardware

The Problem Space

When we began designing THATTE-OS, the question wasn't "how do we port Linux to ternary?" It was: if you had balanced ternary hardware from day one, what would an OS look like?

The answer turns out to be cleaner than binary operating systems in several ways — primarily because ternary maps naturally to three-level privilege systems, three-phase scheduling, and three-state status flags, rather than requiring binary to simulate these multi-state concepts with multiple bits.

THATTE-OS is a microkernel rather than a monolithic kernel. The reasons are practical: for a research platform demonstrating ternary computing principles, a microkernel keeps the trusted computing base small, makes the privilege domain system explicit, and makes it easier to reason about correctness. The full-featured OS implementation can come later.

The T3ISA — Ternary Instruction Set Architecture

An operating system is inseparable from its instruction set. THATTE-OS is written in ManiT assembly targeting the T3ISA — a ternary instruction set designed to run on the PANINI processor (Patent P7).

The T3ISA has several properties chosen specifically for OS development:

• Ternary registers: all registers hold balanced ternary values, with explicit width in trits
• Current-direction-aware load/store: memory addresses are balanced ternary, TritFS-aligned
• TSYS / TRET instructions: privileged syscall entry and return, with privilege-level checking
• TBRZ / TBRNZ / TBRP / TBRN: conditional branches on zero, non-zero, positive, negative trit values
• TMAJ3 as hardware instruction: the ternary majority gate available directly as a CPU opcode

A Note on Trit Registers

T3ISA registers are 27 trits wide — 3³ = 27 — giving each register a range of ±(3²⁷ − 1)/2. The choice of 27 is deliberate: it is a power of 3, making trit-aligned arithmetic natural, and it is wide enough for current address spaces while being symmetric around zero.

Privilege Domains: Three Levels, Not Two

Most binary architectures define two privilege levels — kernel and user — with some adding a third (hypervisor). The choice of two is partly historical (binary hardware), partly practical (most OS theory was developed assuming two levels).

THATTE-OS defines three privilege levels, one per trit state:

The three-level design is not just aesthetic. Supervisor mode exists for device drivers: they need more than user-mode access (direct device I/O) but should not have full kernel privileges (they shouldn't be able to remap the kernel stack or mask critical interrupts). In binary kernels, this is typically solved by running drivers in kernel mode anyway, which is a known security problem. THATTE-OS enforces the separation in hardware.

The 4-Entry Status Register

THATTE-OS uses a 4-entry status register — four trit-width fields — encoding the current execution state:

Status Register: [PRIV | SCHED | IRQ | IO]

  PRIV  : −1 (kernel) | 0 (supervisor) | +1 (user)
  SCHED : current scheduler slot (0, 1, or 2 of three round-robin slots)
  IRQ   : interrupt mask state (−1 masked | 0 partial | +1 enabled)
  IO    : I/O privilege (−1 blocked | 0 polled | +1 interrupt-driven)

The 4-field design means the complete execution context is represented in 4 trits — 81 possible combinations — far more expressive than a typical 32-bit binary FLAGS register where most bits are redundant or reserved.

Boot Sequence

The boot sequence is implemented in boot.t3b (compiled from boot.t3s ManiT assembly). It runs at privilege level −1 (kernel) from power-on:

; boot.t3s — THATTE-OS boot loader
; Entry point: 0x0T00 (ternary address)

BOOT_ENTRY:
    ; Set up ternary stack pointer
    TLOAD   sp, #[STACK_TOP]      ; load stack top address (ternary)

    ; Initialize status register: kernel privilege
    TLOAD   r0, #[-1]             ; PRIV = −1 (kernel)
    TLOAD   r1, #[0]              ; SCHED = 0 (slot 0)
    TLOAD   r2, #[-1]             ; IRQ = −1 (masked during boot)
    TLOAD   r3, #[-1]             ; IO = −1 (blocked during boot)
    TSTAT   r0, r1, r2, r3       ; write status register

    ; Call kernel init
    TCALL   KERN_INIT

    ; Should not return
    THALT

The kernel init (init.t3b) runs next, loading the remaining kernel modules in order and setting up the interrupt vector table (27 entries — one per ternary trit combination for a 3-bit interrupt number space).

The Scheduler: Modulo-3 Round-Robin

The PANINI processor's modulo-3 clock provides three time slots per clock cycle: φ₀, φ₁, φ₂. THATTE-OS's scheduler is built around this: a modulo-3 round-robin where up to three processes share the three time slots.

This is not an arbitrary design choice. The hardware scheduler in PANINI is also modulo-3, so the OS scheduler and hardware scheduler are phase-aligned — context switches can occur precisely at the φ₀ boundary without additional interrupt overhead.

; sched.t3s — round-robin scheduler tick
; Called at φ₀ boundary

SCHED_TICK:
    ; Read current slot from status register
    TSTAT_READ  r0, SCHED_SLOT   ; r0 = 0, +1, or −1... wait, 0/1/2

    ; Increment and wrap modulo-3
    TADD    r0, r0, #[+1]        ; increment slot
    TCMPN   r0, #[MAX_SLOT]      ; compare with max (2 in ternary: +1·0+0·... )
    TBRP    r0, .wrap            ; if positive (overflow), wrap
    TJUMP   .save_slot

  .wrap:
    TLOAD   r0, #[0]             ; reset to slot 0

  .save_slot:
    TSTAT_WRITE  r0, SCHED_SLOT
    TCALL   CONTEXT_SWITCH

Interrupt Handling

The interrupt vector table contains 27 entries — the ternary cube of a 3-trit interrupt number — allowing 27 distinct interrupt sources to be handled independently. This is implemented in irq.t3b:

• Interrupts 0–8 (trits 00−, 00·, 00+, 0−0, ...): hardware exceptions
• Interrupts 9–17: device interrupts (I/O completion, timer, etc.)
• Interrupts 18–26: software interrupts and syscall dispatch

The 27-entry table is not wasted: in a full ternary system with ternary peripheral addressing, 27 interrupt sources maps directly to the 3-trit device address space. No sparse interrupt descriptor table, no PIC/APIC complexity.

The Syscall Interface

User programs call into the kernel via the TSYS instruction with a syscall number in r0. The syscall number is a balanced ternary value, selecting from 27 possible system calls (3³ = 27 with a 3-trit syscall number).

Compiling the Kernel: ManiT v0.1.0

All kernel source files are written in ManiT assembly (.t3s extension) and compiled with the ManiT compiler (Patent P4) to produce .t3b binaries. The full compilation is:

$ manit compile boot.t3s    → boot.t3b    (boot loader)
$ manit compile init.t3s    → init.t3b    (kernel entry)
$ manit compile sched.t3s   → sched.t3b   (scheduler)
$ manit compile irq.t3s     → irq.t3b     (IRQ handler)
$ manit compile proc.t3s    → proc.t3b    (process manager)
$ manit compile syscall.t3s → syscall.t3b (syscall layer)
$ manit compile mem.t3s     → mem.t3b     (TritFS heap)
$ manit compile io.t3s      → io.t3b      (I/O abstraction)

$ manit link *.t3b -o thatte_os.t3b

BUILD COMPLETE: thatte_os.t3b (72 KB, balanced ternary binary)

The compiled binary thatte_os.t3b and all intermediate .t3b files, along with disassembly debug traces (.t3d), are attached as Appendix B to Patent P5. This means the patent itself contains a provably working implementation, not just a description.

What "Running" Means for a Ternary Kernel

At this stage of the project, "running" means the compiled binary has been verified through execution traces: the init sequence executes correctly, the scheduler advances through three slots, interrupt dispatch resolves to the correct vector, and syscall numbers route to the correct handlers. These traces are attached to the patent as proof of operation.

Full emulation on real PANINI hardware awaits fabrication — the next phase of the project. What the kernel implementation proves today is that:

• A ternary OS kernel can be expressed cleanly in ternary assembly
• The three-privilege-level system maps naturally to hardware privilege domains
• A 27-entry interrupt table and 27 syscalls are sufficient for a microkernel
• The ManiT compiler successfully compiles and links all kernel modules