A layer-by-layer technical walkthrough of the balanced ternary computing stack — device physics, gate design, processor architecture, compiler, and microkernel.
Binary computing uses two states (0, 1). Balanced ternary uses three: −1, 0, +1. The key insight is that base-3 is the most efficient radix for information encoding — each digit carries log₂(3) ≈ 1.585 bits of information compared to 1 bit per binary digit.
Crucially, balanced ternary requires no two's complement representation. Negative numbers are represented naturally, and arithmetic operations on balanced ternary numbers are inherently symmetric around zero. Addition, subtraction, and comparison all become simpler.
At the physical level, a three-voltage-rail device maps naturally to balanced ternary. Current flowing in the positive direction is +1; no current is 0; current in the negative direction is −1. This is more natural than the binary trick of using voltage thresholds.
The device channel is a single-wall carbon nanotube (SWCNT) coaxially enclosed within a multi-wall carbon nanotube (MWCNT). This nested geometry achieves two goals simultaneously:
A graphene nanoribbon (GNR) serves as the gate electrode, positioned symmetrically over the SWCNT@MWCNT channel. The bandgap of the GNR is tuned by width to achieve precise ±0.3 V threshold voltages, creating symmetric positive and negative switching behaviour — the physical requirement for balanced ternary.
Unlike conventional transistors with two power rails, the THATTE device operates with three: VDD (+1 V), GND (0 V), and VSS (−1 V). The drain current's direction and magnitude encodes the three trit states, with transitions controlled by gate voltage.
The fabrication process uses chemical vapor deposition (CVD) with benzene (C₆H₆) as the carbon source. Benzene was chosen because its aromatic ring structure provides natural control over chirality during nanotube nucleation — a critical parameter for achieving the precise bandgap needed for ±0.3 V threshold symmetry.
The process proceeds in stages: substrate preparation, catalyst nanoparticle deposition, SWCNT growth under controlled temperature and gas flow, MWCNT overgrowth for coaxial shielding, and GNR gate formation by selective oxidation of a graphene sheet along a lithography-defined nanoribbon.
A notarized affidavit (Exhibit A) establishes that the core device concept was conceived in 2006, providing documentary evidence of priority.
Four standard cells form the basis of the THATTE gate library. Each was designed at the transistor level using THATTE device models and verified by simulation with the Stanford University CNFET SPICE model (Deng & Wong, IEEE Trans. Electron Devices, 2007).
Two complementary THATTE devices in series, one with positive and one with negative threshold. Input +1 → Output −1, Input 0 → Output 0, Input −1 → Output +1. Current symmetry |I(−1)/I(+1)| = 1.0000.
Two devices in series. Output equals the minimum of two trit inputs. Forms the basis of ternary NOR-equivalent logic. Implements min(A, B) = −max(−A, −B) dually.
Three devices in parallel. Output equals the maximum of three trit inputs. Together with TMIN2, allows full ternary combinational logic implementation.
Implements median(A, B, C) — the majority logic gate for balanced ternary. Verified against all 27 possible three-trit input combinations. 27/27 correct.
| A | B | C | median(A,B,C) | Result |
|---|---|---|---|---|
| −1 | −1 | −1 | −1 | ✓ |
| −1 | −1 | 0 | −1 | ✓ |
| −1 | −1 | +1 | −1 | ✓ |
| −1 | 0 | 0 | 0 | ✓ |
| −1 | 0 | +1 | 0 | ✓ |
| −1 | +1 | +1 | +1 | ✓ |
| 0 | 0 | 0 | 0 | ✓ |
| 0 | 0 | +1 | 0 | ✓ |
| +1 | +1 | +1 | +1 | ✓ |
| ... 18 more entries, all verified ... | ✓ | |||
Conventional binary SRAM cells use a 6-transistor bistable flip-flop. The PANINI processor introduces a 3-FET cyclic SRAM cell — a novel topology where three cross-coupled THATTE devices form a cell with three stable states, not two.
Nodes N1 and N2 are cross-coupled through all three voltage rails. The three stable configurations correspond to the three trit values, providing native ternary storage without requiring a binary-to-ternary encoding layer.
A ternary pipeline requires clock phases that divide time into three equal intervals. The PANINI processor implements a modulo-3 clock generator built from TMAJ3 gates and cyclic feedback, producing φ₀, φ₁, φ₂ phases used for three-stage pipeline control.
The ManiT compiler translates balanced ternary assembly source (.t3s files)
to binary-encoded T3ISA machine code (.t3b files). A disassembler
produces human-readable debug output (.t3d files).
Tokenises .t3s source: opcodes, registers, trit literals, labels
Builds AST with instruction types and operand resolution
Emits T3ISA encoding; resolves branch targets, labels
Ternary binary: balanced ternary encoded machine instructions
; ManiT Assembly — T3ISA Example
; Load trit constant +1 into register r0
TLOAD r0, #[+1]
; Load trit constant −1 into register r1
TLOAD r1, #[-1]
; Ternary ADD: r2 = r0 + r1 = 0
TADD r2, r0, r1
; Conditional branch on zero
TBRZ r2, .zero_case
; TMAJ3: majority of r0, r1, r2 → r3
TMAJ3 r3, r0, r1, r2
; Syscall: write trit to output
TSYS 0x01, r3
THATTE-OS is a compiled, running microkernel for balanced ternary hardware.
Written in ManiT assembly, compiled by the ManiT compiler to nine
.t3b binary modules, with full debug traces attached as patent appendices.
The kernel implements three privilege domains — kernel (−1), supervisor (0), user (+1) — one per trit state. Privilege escalation and de-escalation are controlled by the 4-entry status register via dedicated TSYS/TRET instructions.
TritFS addresses all storage resources using balanced ternary. A 5-trit address provides 3⁵ = 243 addressable locations. Memory heap blocks, file system inodes, and network buffers are all allocated using trit-arithmetic operations, eliminating the need for binary-to-ternary address conversion layers.
Appendix C of P8 contains a complete 128-entry ASCII-to-balanced-ternary encoding table, enabling ternary-native text processing in THATTE-OS without binary translation.
A trie where each node has exactly three children, indexed by trit state (−1, 0, +1). Provides O(k) lookup, insert, and delete for trit-encoded keys of depth k. Used by TritFS for directory indexing and by the ManiT compiler for symbol tables.
| Char | ASCII | Balanced Ternary |
|---|---|---|
| A | 65 | +1 −1 −1 +1 −1 |
| M | 77 | +1 0 −1 −1 +1 |
| T | 84 | +1 0 +1 0 0 |