Nine patents covering every layer of the balanced ternary computing stack — from the fundamental device physics to an operating system microkernel. All filed with the Indian Patent Office in March 2026.
The foundational device patent introduces a hybrid carbon nanotube field-effect transistor (CNFET) architecture designed specifically for balanced ternary logic. The device uses a SWCNT@MWCNT channel — a single-wall carbon nanotube coaxially shielded by a multi-wall nanotube — with a graphene nanoribbon (GNR) gate electrode.
Three voltage rails — VDD (+1 V), GND (0 V), VSS (−1 V) — enable natural ternary operation. The device switches symmetrically at ±0.3 V threshold voltages, encoding logic states +1, 0, −1 via the direction and magnitude of drain current.
The MWCNT shielding geometry reduces random telegraph noise (RTN), a critical challenge in nanoscale devices, without compromising the three-state switching behaviour.
This method patent covers the operational principles of the THATTE device — specifically how three logic states are encoded, detected, and maintained. Logic values are encoded via current direction: positive current → +1, zero current → 0, negative current → −1.
The coaxial MWCNT shielding provides a Faraday-cage-like geometry around the SWCNT channel, reducing the charge fluctuation events responsible for RTN. The patent establishes the relationship between shielding geometry and noise immunity as a function of tube diameter ratio.
The fabrication patent details a complete chemical vapor deposition (CVD) process using benzene (C₆H₆) as the carbon precursor. The process is designed to achieve the precise chirality and diameter control needed for ternary symmetry in the SWCNT@MWCNT channel.
Includes a notarized affidavit (Exhibit A) proving conception of the core device concept as early as 2006, establishing priority over subsequent disclosures in the field of nanotube-based logic devices.
A complete standard cell library for balanced ternary IC design, comprising four gate types. Each cell is fully characterized by SPICE simulation using the Stanford CNFET model.
The PANINI processor patent covers a novel CPU architecture built on ternary standard cells. The most significant innovation is the 3-FET cyclic SRAM cell — the first memory cell designed to hold three stable states, with cross-coupled nodes N1 and N2 stabilised through all three voltage rails (VDD, GND, VSS).
The architecture also introduces modulo-3 clock generation, solving the fundamental problem of timing in a ternary pipeline. The clock divides phases into three equal intervals rather than the two used in binary systems.
A complete compiler for the T3ISA (Ternary 3-state Instruction Set Architecture), comprising a lexer, parser, and code generator targeting balanced ternary assembly. Appendix A contains the full compiler specification v0.1.0, dated 21 March 2026, with all three trit states verified in execution traces.
The T3ISA defines instructions operating on trit-width registers, addressing modes compatible with TritFS memory layout, and a syscall interface for THATTE-OS.
A complete balanced ternary operating system microkernel. The patent covers the boot
loader sequence, process scheduler, interrupt handler, and process manager, all
implemented in ManiT assembly and compiled to .t3b binary format.
The kernel uses a 4-entry status register and a privilege domain system
that maps naturally to three privilege levels (kernel, supervisor, user) — one per trit state.
Compiled binaries (boot.t3b, init.t3b, thatte_os.t3b)
and debug traces are included as appendices.
TritFS introduces trit-addressed resource allocation for memory heaps, storage, and network buffers. All addresses are encoded in balanced ternary (5 trits = 3³ = 243 addressable positions). Appendix C provides a complete 128-entry ASCII-to-balanced-ternary encoding table using MST-first balanced ternary conversion.
Filed as a continuation of P8 (earmarked in P8 Claim 9), TritTrie covers an efficient ternary trie where each node branches on three trit states (−1, 0, +1), enabling O(k) search, insert, and delete operations on trit-encoded keys of depth k.
Applications include trit-addressed filesystem indexing (TritFS directories), ternary symbol tables in the ManiT compiler, and efficient routing tables for ternary-addressed network stacks.
Patents build on each other. The recommended filing sequence ensures cross-references can be established at time of filing.
| Order | Patent | Title | Depends On | Status |
|---|---|---|---|---|
| 1 | P1 | THATTE Structure | — | Filed |
| 2 | P2 | Switching Method | P1 | Filed |
| 3 | P3 | Fabrication | P1, P2 | Filed |
| 4 | P6 | Gate Library | P1, P2 | Filed |
| 5 | P7 | PANINI Processor | P6 | Filed |
| 6 | P4 | ManiT Compiler | P7 | Filed |
| 7 | P5 | THATTE-OS | P4, P7 | Filed |
| 8 | P8 | TritFS | P4, P5 | Filed |
| 9 | P9 | TritTrie (continuation) | P8 | Filed |