Browse the balanced ternary instruction set architecture. Click a category to view its instructions, then click an instruction for encoding details.
Each instruction is encoded in a fixed-width 27-trit word. The field layout above shows the general R-type format. Some instruction classes use alternate field arrangements (e.g., branch instructions may encode a wider address field). The 27-trit width equals 33 = one ternary "word" in the T3ISA convention.
The status register encodes processor state using balanced ternary flags. Each field uses trit values −1, 0, +1 to represent three-valued conditions (e.g., PRIV: kernel / supervisor / user).