Why AC, Not DC:
The Transmission Line Paradigm

The Trap of Thinking in Binary

If you have spent any time around transistor design, your instincts have been shaped by a very specific mental model: a gate voltage controls a channel. Apply voltage, the channel conducts. Remove voltage, it stops. One means current flows. Zero means it does not. This is the MOSFET worldview, and it has been the foundation of computing for over sixty years.

The problem is not that this model is wrong — it works brilliantly for silicon CMOS. The problem is that it is so deeply ingrained that we unconsciously apply it to every new device, even when the physics does not call for it. When researchers propose ternary computing, the first question is almost always: how do you create a third voltage level? The assumption is that you need three DC states controlled by a gate. A low voltage for −1, a mid voltage for 0, a high voltage for +1. Three levels, three thresholds, three noise margins to worry about.

This is a trap. It imports the hardest problems of binary scaling — threshold voltage control, leakage current management, noise margin erosion — and makes them worse by adding a third state. Every serious ternary proposal based on DC multi-level signalling has run into the same wall: the noise margins become unacceptably thin when you try to squeeze three distinguishable voltage levels into a supply range that already struggles with two.

The THATTE device sidesteps this entirely. It does not use three voltage levels. It does not use DC at all.

The Binary Mindset: How CMOS Trained Us

In CMOS logic, information encoding works like this: a transistor is either on or off. The gate voltage determines which state. The drain current is a consequence of the gate voltage. The signal path is: gate voltage → channel conductance → drain current → output voltage. At every stage, the signal is a DC quantity — a static voltage level that represents a bit.

This architecture has a specific set of constraints. The gate must swing between well-defined voltage thresholds. The channel must transition cleanly between conducting and non-conducting states. The output voltage must be unambiguously above or below a decision threshold. Everything is about levels — static, DC, held in place by charge on a capacitor.

When you try to extend this to three states, you need two thresholds instead of one, three level bands instead of two, and the gate voltage must select among three distinct conductance regimes. The gate dielectric must be pristine. The threshold voltage must be controlled to millivolt precision. Process variation becomes a nightmare.

But what if the signal is not a voltage level at all?

What a Transmission Line Actually Is

A metallic single-walled carbon nanotube — the SWCNT at the heart of the THATTE device — is not a semiconductor channel. It is a one-dimensional ballistic conductor. Electrons travel through it without scattering, at a significant fraction of the Fermi velocity, over distances of hundreds of nanometres to micrometres. There is no gate-controlled barrier. There is no depletion region. There is no threshold voltage.

In radio-frequency engineering terms, this is a transmission line. It has a characteristic impedance (~6.5 kΩ per quantum channel, set by the quantum of conductance). It supports wave propagation. Signals travel along it as guided electromagnetic modes, not as drift current through a resistive medium.

The distinction matters enormously. A resistive channel dissipates energy as current flows through it. A transmission line propagates signals with minimal loss. A resistive channel has an RC time constant that limits switching speed. A ballistic transmission line does not — its speed is limited by the wave propagation time, which at nanotube dimensions is in the sub-picosecond regime.

This is the first conceptual shift: the SWCNT is not a switch that you turn on and off. It is a wire — an extraordinarily good wire — that is always ready to carry a signal. The question is not whether it conducts, but what signal you put on it.

AC Gives You Three States for Free

Consider an AC waveform on a transmission line. At any given moment, the instantaneous signal is in one of three regimes:

• Positive phase: current flows in the forward direction
• Zero crossing: current is momentarily zero
• Negative phase: current flows in the reverse direction

These are not three artificially constructed voltage levels. They are the natural, inherent states of any AC waveform. Positive. Zero. Negative. The three values of a balanced ternary trit.

The trit sequence follows the waveform: +1, 0, −1, 0, +1, 0, −1, 0… — a palindrome. The signal always passes through zero between positive and negative phases. There is never a direct transition from +1 to −1. The zero state is not an afterthought or a constructed midpoint; it is the natural rest state that the waveform passes through on every cycle.

This is why AC, not DC. In the DC paradigm, you must engineer three voltage levels and maintain them against noise. In the AC paradigm, the three states already exist — they are properties of the waveform itself. You do not create them. You read them.

In DC thinking, you need a gate to create three states.
In AC thinking, you already have three states from the waveform itself.

The Zero That Means Zero

The zero state deserves special attention, because it is the most misunderstood aspect of the paradigm.

In a DC ternary device, the zero state is a voltage level — typically V_DD/2. It is actively maintained by the circuit. It consumes power. It must be distinguished from both V_DD and ground by comparators with finite noise margins. It is not zero in any physical sense; it is a biased midpoint.

In the THATTE device, trit 0 is the absence of signal. No photon is present. No AC voltage is applied. No current flows. The metallic SWCNT sits at its equilibrium state, always ready to carry a signal but carrying none. The measured current in the zero state is the thermal noise floor — well below the digital-grade signal current of the active trit states.

This is a true zero. It is not a constructed level between two other levels. It is not maintained by a circuit. It is the natural state of a conductor with nothing to conduct. And because it is true absence rather than a biased midpoint, it is trivially easy to distinguish from the active states. The signal- to-noise ratio is well above the threshold for reliable digital switching — multiple orders of magnitude. There is no ambiguity.

This eliminates the tightest constraint in DC ternary design: the requirement for a stable, precisely centred middle voltage that must be distinguished from two adjacent levels. In the AC paradigm, the zero state distinguishes itself — it is the only state where nothing is happening.

Light as Gate, Current as Signal

The THATTE device has three independent inputs: two photon wavelengths and one AC electrical signal. This is where the paradigm becomes fully photonic-ternary.

A gate photon is optically coupled to the device. The photon does not “switch” the device in the CMOS sense. It does not create or destroy a conducting channel. The SWCNT is always conducting — it is metallic. What the photon does is gate it. It is a modulation, not a switch, and the mechanism is specification-level detail, available under NDA.

The AC signal on the SWCNT terminals then determines the current direction. Positive AC phase gives a digital-grade signal current (trit +1). Negative AC phase gives the same magnitude in reverse (trit −1). No photon and no AC gives true absence of signal (trit 0). The symmetry is essentially perfect: I(+V) = −I(−V), verified by NEGF simulation.

A second photon at a different wavelength can independently address the SWCNT itself, enabling a dual-photon mode where a single device encodes multiple distinguishable states — wavelength-division multiplexing at the nanotube scale. Full operating parameters and wavelength specifications are available under mutual NDA.

The signal path in this paradigm is fundamentally different from CMOS:

The “gate” is light, not voltage. The “channel” is a transmission line, not a resistive switch. The “output” is a signed current, not a voltage level.

Speed Without RC Delay

In CMOS, switching speed is limited by RC delay — the time it takes to charge or discharge the gate capacitance through the channel resistance. As transistors shrink, the capacitance decreases but the resistance increases, and the product stays stubbornly finite. Modern silicon logic tops out at a few GHz for practical circuits, despite decades of optimisation.

The THATTE device does not have this limitation. The SWCNT is a ballistic conductor — there is no channel resistance in the conventional sense. The speed limit is set by a different physical process entirely: hot-carrier relaxation, the time it takes for photo-excited electrons in the MWCNT to return to equilibrium after absorbing a photon.

In carbon nanotubes, hot-carrier relaxation occurs on the sub-picosecond to few-picosecond timescale. This corresponds to a maximum trit rate multiple orders of magnitude beyond the clock rates achievable with silicon CMOS.

Furthermore, because the three inputs (two photons and the AC signal) are independent and operate at their own clock rates, the effective data rate can exceed any single input’s frequency through interleaving. The photon clock and the AC clock can be phase-locked, harmonically locked, or run at beat frequencies.

This is not a theoretical extrapolation from device physics alone. The NEGF (non-equilibrium Green’s function) quantum transport simulation of the SWCNT@MWCNT structure confirms the operating point: digital-grade switching current, signal-to-noise ratio well above the threshold for reliable switching, perfect current symmetry. The device is not marginal. It is a clean digital switch with enormous signal margin.