RTN Shielding: Quantifying Noise
Reduction in Coaxial CNT Channels

What Is Random Telegraph Noise?

Random telegraph noise (RTN) is a phenomenon observed in nanoscale transistors where the drain current fluctuates randomly between two or more discrete levels. The name comes from the waveform's resemblance to a telegraph signal — abrupt jumps between fixed levels with random timing.

The physical mechanism is well understood. At nanometre scales, individual charge traps near the channel — typically at the oxide-semiconductor interface or within the gate dielectric — can capture and release single electrons. Each capture/release event changes the local electrostatic environment of the channel, shifting the threshold voltage by a discrete amount and causing the drain current to jump between levels.

In bulk silicon devices with millions of charge carriers, these single-electron events average out and become invisible. But in a carbon nanotube FET — where the channel is a single tube with a diameter of 1–2 nm and the current is carried by a small number of charge carriers — a single trapped charge can shift the threshold voltage by tens of millivolts. This is not a theoretical concern; it is a measured, documented phenomenon in CNFET literature.

Why RTN Is Worse for Ternary

A binary transistor needs to distinguish two states: on and off. The noise margin is the voltage difference between the two states minus the minimum voltage needed to reliably distinguish them. With a 1 V supply and two states, the separation is approximately 1 V.

A ternary transistor must distinguish three states: −1, 0, and +1. With the same 1 V supply range (from −1 V to +1 V), the separation between adjacent states is approximately 1 V — but there are two boundaries instead of one, and the middle state (0 V) must be distinguished from both its neighbours.

The practical consequence is that a ternary device must have lower absolute noise than a binary device of the same supply voltage to achieve equivalent reliability. Any RTN-induced threshold voltage shift that causes the output to cross a decision boundary results in a trit error — the wrong value is read.

The Faraday Cage Principle

The Faraday cage is one of the oldest and most reliable electromagnetic shielding mechanisms, known since Michael Faraday's experiments in 1836. The principle is simple: a conductive enclosure blocks external electric fields from reaching its interior. This is why sensitive electronics are placed in metal enclosures, why MRI rooms have copper mesh in the walls, and why your microwave oven does not irradiate your kitchen.

The relevance to CNFETs becomes clear when you consider the geometry of the THATTE device. The channel is a single-wall carbon nanotube (SWCNT) located inside a multi-wall carbon nanotube (MWCNT). This SWCNT@MWCNT coaxial geometry — a conducting inner tube surrounded by a conducting outer tube — is, topologically, a nanoscale Faraday cage.

The SWCNT@MWCNT coaxial structure has been synthesised and characterised in published materials science research. Groups at NEC, Rice University, and others have demonstrated "peapod" and coaxial nanotube structures since the early 2000s. The physics of the shielding effect in such structures is governed by standard electrostatics.

RTN Sources and Shielding

The primary RTN sources in a CNFET are:

• Interface traps: Charge traps at the CNT-dielectric interface. These are the dominant RTN source in most CNFET devices.
• Oxide traps: Defects within the gate dielectric (HfO₂ in our case) that can capture and release carriers.
• Substrate coupling: Electric field fluctuations from the substrate or neighbouring devices coupling into the channel.

A coaxial channel geometry addresses the third source directly — the outer tube acts as an electrostatic shield, attenuating external field fluctuations before they reach the inner channel. The first two sources are inherent to the device's own interfaces and require materials engineering to address, but the third source — which can be significant in dense circuit layouts — is geometrically suppressed.

The specific shielding mechanism, the quantitative noise reduction, and how the coaxial geometry is integrated into the THATTE device structure are the subject of Patents P1 and P2. What I present here is the publicly known physics of coaxial shielding applied to the publicly known SWCNT@MWCNT geometry.

What the SPICE Numbers Tell Us

In the SPICE verification post, we reported two measurements that are directly relevant to noise performance:

The 2.01 pA Leakage

The leakage current of 2.01 pA at the zero state (V_in = 0 V) is approximately five orders of magnitude below the switching current (~28 mA). This extremely low leakage means the zero state is well-defined — there is negligible current flow when the device should be in the "off" (zero trit) state.

For RTN analysis, low leakage at the zero state means that noise-induced current fluctuations in the off state are starting from an extremely low baseline. Even if RTN causes a relative current change of 10x at the zero state, the absolute current (20 pA) is still five orders of magnitude below the on-state current. The decision boundary between "zero" and "non-zero" is well-protected.

The 1.0000 Current Symmetry

Perfect current symmetry between the +1 and −1 states means the two active states are equally well-defined. If the device had asymmetric drive strength — say, 30 mA for +1 but only 20 mA for −1 — then the −1 state would be more vulnerable to noise (less current margin above the decision boundary).

A symmetry ratio of 1.0000 means both active states have identical noise margins. This is critical for balanced ternary, where the sign of the current (positive vs. negative) encodes information. Any asymmetry would make one trit value inherently less reliable than the other.

Why This Matters for Product Viability

A ternary computing device that works in simulation but fails due to noise in fabrication is worthless as a commercial product. The semiconductor industry has extremely stringent reliability requirements — particularly for SRAM, where a single cell failure can corrupt data.

The SPICE results establish that the THATTE device, as modelled, has the electrical characteristics needed for reliable three-state operation:

• Clean separation between all three states
• Symmetric drive strength for balanced operation
• Extremely low leakage at the zero state
• Threshold voltage symmetry at ±0.3 V

The coaxial SWCNT@MWCNT geometry provides an additional noise defence layer that is inherent to the device structure — it does not require external shielding, additional circuitry, or error correction overhead. This structural approach to noise reduction is one of the distinguishing features of the THATTE device compared to other CNFET designs in the literature.

Next Steps: Monte Carlo Analysis

The SPICE results presented so far are nominal — they represent the device operating at exactly the designed parameters (300 K, nominal chirality, ideal geometry). Real fabricated devices will have process variations: tube diameter distribution, chirality mix, gate dielectric thickness variation, and temperature corners.

Monte Carlo SPICE analysis — running thousands of simulations with randomly varied parameters — is the standard method for quantifying the impact of process variation on circuit performance. This is the next planned verification step, and results will be reported in a future post.