PANINI Processor: Designing a
Ternary SRAM Cell

Why SRAM Is the Foundation

Every processor ever built depends on SRAM. Register files, L1 caches, L2 caches, TLBs, branch prediction tables, reorder buffers — all of these are SRAM arrays. The performance of a processor is, to a first approximation, the performance of its memory hierarchy. And the memory hierarchy starts with SRAM.

When we set out to design the PANINI processor — a balanced ternary microarchitecture executing T3ISA instructions — the first question was not "how many pipeline stages?" or "what is the clock frequency?" It was: can we build an SRAM cell that reliably stores three states?

Without a working ternary SRAM cell, there is no register file. Without a register file, there is no processor. Everything depends on this one circuit element.

The Binary SRAM Problem

The standard binary SRAM cell — the "6T cell" — uses six transistors arranged as two cross-coupled inverters plus two access transistors. The cross-coupled inverters form a bi-stable latch: two stable states, corresponding to logic 0 and logic 1. This design has been the industry workhorse since the 1960s, scaled from microns to nanometres, and is among the most well-characterised circuits in existence.

The key word is bi-stable. Two stable states. For ternary logic, we need tristable — three stable states.

The naive approach would be to add more transistors to the 6T cell to create a third stable point. Published literature has explored this: 8T cells, 10T cells, even 12T cells with additional feedback paths or multi-threshold devices. These approaches work in simulation, but they share a common problem: more transistors means larger die area, higher leakage power, and slower access time.

The Three-State Stability Challenge

Creating three stable states in a memory cell is fundamentally harder than creating two. In a bi-stable latch, the positive feedback loop has exactly two equilibrium points — the transfer characteristics of the two inverters cross at two stable points and one unstable midpoint. The unstable point is rejected by the circuit dynamics: any perturbation pushes the cell toward one of the two stable states.

For tristable operation, you need the transfer characteristic to cross at three stable points and two unstable points. This requires a non-linear transfer function with specific shape — the kind of S-curve that binary CMOS inverters simply do not produce.

This is where the properties of the THATTE device become essential. Carbon nanotube FETs with the specific geometry and threshold characteristics described in Patents P1 and P2 exhibit a transfer function that naturally supports three equilibrium points when configured in the right feedback topology.

What We Achieved: 3 FETs, 3 States

The PANINI processor's SRAM cell uses only three THATTE FET devices to achieve tristable operation. I will not describe the circuit topology here — that is the subject of Patent P7, Claim 4 — but I can state the result.

The 3-FET ternary SRAM cell stores one trit (three states: −1, 0, +1) using three transistors, compared to six transistors for a single bit in conventional binary SRAM. This represents a 2x reduction in transistor count per unit of information stored (1.585 bits/trit vs. 1 bit/cell).

The implications are significant. In a 27-trit register (the T3ISA register width), the register file requires 27 x 3 = 81 transistors per register. A comparable binary register file storing the same information range would need approximately 43 bits (since 2⁴³ is approximately 3²⁷), requiring 43 x 6 = 258 transistors. That is a 3.2x reduction in transistor count for equivalent information capacity.

The Modulo-3 Clock

Ternary hardware naturally maps to three-phase operation. This is not a novel concept — three-phase clocking has been used in dynamic logic since the 1970s, and three-phase electrical power distribution has been standard since the 1890s. What is different in the PANINI context is that the three phases correspond directly to the three trit states.

The PANINI processor uses a modulo-3 clock with three phases: phase 0, phase 1, and phase 2. Each phase corresponds to one stage of the three-stage pipeline. During each clock phase, one pipeline stage is active. After three phases, all three stages have executed once, and the cycle repeats.

PANINI Pipeline — Modulo-3 Clock Mapping

  Phase 0 (clock = 0):  FETCH   stage active
  Phase 1 (clock = +1): EXECUTE stage active
  Phase 2 (clock = -1): WRITE   stage active

  → Three instructions in flight simultaneously
  → One instruction completes per clock phase
  → No binary clock divider needed — the trit IS the phase

The elegance of this design is that the clock signal itself is a balanced ternary value cycling through {0, +1, −1}. There is no separate "phase decoder" — the pipeline stage selection is the clock trit, read directly by the SRAM access logic and the pipeline control registers.

From SRAM Cell to Register File

The PANINI processor defines a register file with the following structure:

The total SRAM requirement for the register file is: (11 x 27 + 4) = 301 trits, or 301 x 3 = 903 transistors. A binary register file of equivalent information capacity would require roughly 2,900 transistors. The 3-FET cell delivers a substantial area and power advantage at the most performance-critical point in the entire processor.

Why This Matters Commercially

Memory IP is among the most valuable intellectual property in the semiconductor industry. Companies like ARM and Synopsys derive significant revenue from licensing SRAM compiler IP — the tools and cell libraries that generate optimised SRAM arrays for specific process nodes.

A ternary SRAM cell that achieves three stable states with fewer transistors than the binary 6T cell stores per bit represents a fundamental advantage. If ternary computing gains traction — through carbon nanotube technology or other three-state device technologies — the SRAM cell design will be required by every processor, cache, and memory-intensive circuit built on that technology.

This is why Patent P7, Claim 4 (the 3-FET SRAM cell) is identified as the highest commercial value claim in the entire THATTE portfolio. It is not just a component of the PANINI processor — it is a foundational building block for any future ternary digital system.

The Broader PANINI Architecture

The SRAM cell is one piece of the PANINI processor, which also defines:

• A three-stage pipeline (Fetch / Execute / Write-back) clocked by the modulo-3 clock
• A ternary ALU implementing TINV, TMIN, TMAX, TMAJ, and ternary arithmetic
• A trit-addressed memory interface compatible with TritFS (Patent P8)
• Hardware privilege enforcement for the three THATTE-OS privilege levels
• 27-entry interrupt vector table, hardware-decoded from 3-trit interrupt numbers

The full microarchitecture specification is the subject of Patent P7. What I have shared here is the motivation and result for the SRAM cell specifically — because it is the component that makes everything else possible.