From 9 Provisionals to 6 Complete Specs:
Consolidating the Patent Stack

Why 9 Became 6

In March 2026, we filed nine provisional patent applications with the Indian Patent Office. Each one carved out a specific piece of the balanced ternary computing stack: the device structure, the switching method, the fabrication process, the compiler, the operating system, the gate library, the processor architecture, the file system, and the trie-based data structure. Nine provisionals, nine distinct ideas, nine application numbers.

Six weeks later, on 9 April 2026, we filed six complete specifications. Not nine. Six. And the reduction was not about saving filing fees or reducing paperwork. It was about something more fundamental: in the weeks between the provisionals and the complete specs, our understanding of the architecture changed so profoundly that the original nine-way partition no longer made sense.

The consolidation was driven by a paradigm shift in the device physics itself. Once the device changed, everything above it — logic, processor, memory, software — had to be re-examined from first principles. When we did that, the natural groupings turned out to be different from what we had assumed in March.

The Original Nine

Each provisional application covered a specific concept in the stack. In brief:

The codenames were drawn from the Dashavatara — the ten avatars of Vishnu in Hindu tradition. Each avatar represents a stage in the evolution of complexity, from the primordial (Matsya, the fish) to the transcendent (Kalki, the final avatar). The naming was not decoration. It reflected a genuine belief that the stack follows an evolutionary arc: from the simplest physical device to the most abstract software layer.

These codenames remain. They are the conceptual identity of the ideas. But they are no longer the filing units.

The Paradigm Shift

Between the provisional filings in March and the complete specifications in April, three things changed simultaneously:

First, the device structure simplified. The original provisional described a four-layer concentric structure. By April, simulation work had shown that a two-layer structure — an inner single-wall carbon nanotube inside an outer multi-wall carbon nanotube — was sufficient. Fewer layers, cleaner physics, stronger claims.

Second, the tube type changed. The provisionals assumed a semiconducting nanotube as the active channel. The complete specifications use a metallic armchair nanotube — a fundamentally different kind of conductor. This was not a minor parameter tweak. It changed the operating principle of the device.

Third, the switching mechanism changed. The provisionals described a DC gate-controlled field-effect transistor in the classical sense. The complete specifications describe something different: an AC-driven, photon-gated switching mechanism where the trit value is encoded in the polarity of an AC pulse, not in the state of a DC gate. This is a different kind of device entirely.

Each of these changes, taken alone, would have required rewriting the relevant provisional. Taken together, they demanded a rethinking of where the boundaries between patents should fall.

The Consolidation Logic

The key insight was that certain provisionals were no longer separable. Once the device structure, the switching method, and the fabrication process all depended on the same two-layer photonic architecture, it made no sense to file them as three separate patents. They were three views of one invention.

Thatte1 (Device) is the most significant consolidation. The device structure (P1), the switching method (P2), and the fabrication process (P3) were originally filed as separate provisionals because, in March, we thought they could vary independently. A different structure might use the same switching method. A different fabrication route might produce the same structure. But after the paradigm shift, these three aspects became tightly coupled. The two-layer structure is the switching mechanism. The fabrication route determines the structure. Three provisionals became one complete specification because the physics demanded it.

Thatte2 (Logic) absorbed the gate library from P6 and expanded it with a complete arithmetic engine. The logic layer sits between the device and the processor — it defines how individual switching elements combine into computational primitives. In the provisional era, this was just a gate library. In the complete spec, it includes the full arithmetic framework that the processor depends on.

Thatte3 (Processor) remained close to P7 in scope. The processor architecture — codenamed PANINI — was already well-defined in the provisional. The complete specification updated the implementation details to reflect the new device physics, but the architectural boundaries stayed the same.

Thatte4 (Memory & Interconnect) merged TritFS (P8) and TritTrie (P9) with a new interconnect and bus fabric layer. In the provisionals, the file system and the trie data structure were filed separately because they seemed like independent inventions. But when we designed the memory subsystem for the complete spec, it became clear that the file system, the address trie, and the bus fabric are all parts of one coherent memory management architecture. They share addressing schemes, they share data formats, and they share the same balanced ternary encoding conventions. One patent covers all of it.

Thatte6 (Software) combined the ManiT compiler (P4) and THATTEOS (P5). A programming language and its target operating system are deeply intertwined — the system call interface, the memory model, the process abstraction. Filing them as one specification allowed us to define the software stack as a coherent whole rather than two halves that reference each other.

What Thatte5 Added

Thatte5 — Security and Test — has no provisional ancestor. It is entirely new.

The provisionals filed in March covered the functional stack: how to build the device, how to compute with it, how to program it. What they did not cover was how to verify it and how to secure it.

Between March and April, two things became clear. First, balanced ternary arithmetic has properties that can be utilized for cryptographic operations in ways that binary arithmetic cannot. The three-valued logic creates a richer algebraic structure. Second, any serious hardware patent portfolio needs to address design-for-test (DFT) and built-in self-test (BIST) — the mechanisms by which a manufactured chip verifies its own correctness.

Thatte5 covers both: the cryptographic hardware layer and the test infrastructure. These are architecturally distinct from the processor (Thatte3) and the memory (Thatte4), so they warranted their own specification. This is the one case where consolidation actually increased the total number of filings — from zero provisionals covering security to one complete specification dedicated to it.

Filing Day: 9 April 2026

All six complete specifications were filed with the Indian Patent Office on 9 April 2026. Each filing included the full specification text, the claims, the abstract, and supporting simulation evidence. The filing fees were paid, the application numbers were assigned, and the twelve-month clock for international filing under the Patent Cooperation Treaty started ticking.

The Dashavatara codenames remain as the conceptual identity of the ideas. MATSYA is still the device. RAMA is still the processor. NARASIMHA is still the compiler. But the legal filings — the documents that define the intellectual property — are Thatte1 through Thatte6. Six specifications. Six application numbers. One coherent stack.

The consolidation was not a reduction. It was a clarification. Nine ideas did not become six ideas. Nine filing boundaries became six filing boundaries, because that is where the architecture actually divides.