Technical writeups, experiment logs, and design rationale from the development of the THATTE balanced ternary computing system.
Generic MOSFET wrappers hide the real physics of novel devices. When your simulation gives a perfect 1.000 symmetry ratio, the question is not whether the device works — it is whether your model is telling you the truth. This is the story of replacing a borrowed model with one built from the ground up.
Why generic transistor models hide the real physics of novel devices, and how the RAVAN compact model replaces a MOSFET wrapper with Landauer transport, Fermi-Dirac statistics, and first-principles temperature dependence.
Random telegraph noise in nanoscale transistors, why ternary devices have tighter noise margins, and what the SPICE measurements reveal about the THATTE device's noise resilience.
Why binary code cannot run on ternary hardware, the design space for a ternary ISA, and what compiling the THATTE-OS kernel to 72 KB of .t3b binaries proved.
The publicly known science of chemical vapour deposition, the chirality problem in CNT synthesis, and how a 2006 priority date anchors the THATTE fabrication patent.
What changes when storage addresses use trits instead of bits — inode design, ternary bitmaps, trit-state journalling, and the ASCII encoding challenge in balanced ternary.
Why traditional 6T SRAM cannot store three states, what a 3-FET ternary memory cell achieves, and why compact SRAM is the most commercially valuable piece of the PANINI processor.
How we used ngspice with the Stanford CNFET model to verify every gate in the library — from inverter symmetry to the 27-entry majority gate truth table. What the numbers mean and why they matter for real fabrication.
Design decisions behind a balanced ternary microkernel — from privilege domains to the T3ISA syscall interface. How the ManiT compiler makes it compile, and what a ternary boot sequence looks like.
The mathematical elegance of base-3, natural signed-number representation without two's complement, and the physical case for three voltage levels in carbon nanotube FET devices. Why now?
New posts on balanced ternary devices, SPICE experiments, and patent progress. Contact manish@maniTLab.org to be added to the mailing list.
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