maniTLab · Nashik, India · 2026

The Inventor
& the Lab

The story behind the THATTE balanced ternary computing project — from a 2006 insight to a nine-patent portfolio filed with the Indian Patent Office.

Manish Jagdish Thatte
Manish Jagdish Thatte
Inventor · Researcher
Nashik, Maharashtra, India
Patent Filing Status
Total Patents9
FiledMarch 2026
OfficeIPO India
Priority date2006
Complete specBy Mar 2027
Technology Areas
NanotechnologyCNFET · GNR
Computer ArchitectureTernary CPU
CompilersT3ISA · ManiT
Operating SystemsTHATTE-OS
VLSI DesignStandard Cells

Manish Jagdish Thatte

I am an independent inventor and researcher based in Nashik, Maharashtra, India. My work focuses on alternative computing paradigms — specifically balanced ternary computing — from the transistor level through to operating systems and compilers.

The THATTE project represents twenty years of work on a single question: what would a computer look like if it had been designed from first principles around three logic states, not two?

The 2006 Insight

In 2006, while studying the behaviour of carbon nanotube devices in the literature, I noticed something that seemed obvious in retrospect but had not been systematically pursued: a CNFET can conduct current in either direction with equal symmetry, making it a natural three-state device. Positive current, zero current, negative current — three states, not two.

The implications were immediate: if the device is naturally three-state, build a three-state logic family around it. And if you are building a three-state logic family, balanced ternary is the mathematically optimal encoding. From there, the entire stack unfolds: gates, standard cells, processor, compiler, operating system.

This insight is documented in a notarized affidavit (Exhibit A, attached to Patent P3), establishing the 2006 conception date for the core THATTE device concept. The affidavit was executed before a notary public on 21 March 2026 as part of the patent filing process.

Lab Mission

maniTLab exists to prove that balanced ternary computing is not a historical curiosity or an academic exercise. It is a practical, physically realisable alternative to binary that becomes increasingly attractive as binary scaling approaches its limits.

The mission has three phases:

1

Establish the Patent Portfolio

Nine patents filed with IPO India, covering the complete hardware-to-software stack. Complete spec by March 2027.

Done
2

Physical Device Demonstration

Fabricate the THATTE CNFET device and demonstrate three-state switching in the lab. Validate SPICE results experimentally.

Next
3

Open Licensing & Collaboration

License the technology to semiconductor fabs, EDA vendors, and research institutions. Build the ternary computing ecosystem.

Future

Proof of Work

The THATTE project is unusual in that it does not just describe a system — it delivers working implementations at every layer:

  • SPICE simulation: ngspice-44.2 with Stanford CNFET model, all gates verified
  • Compiled kernel: THATTE-OS 0.1.0 compiles to .t3b binaries with full execution traces
  • Working compiler: ManiT v0.1.0 compiles all kernel modules successfully
  • Encoding table: 128-entry ASCII-to-balanced-ternary table verified
  • Patent documents: 9 × FINAL.pdf, 24 technical figures, SPICE output files — 31 filed documents

This level of implementation detail in a patent filing is uncommon. It reflects a deliberate choice: to make the inventions undeniable, not just describable.

Press & Contact

For research collaboration, licensing enquiries, technical questions, or press requests, contact:

Manish Jagdish Thatte
Independent Inventor · maniTLab
Nashik, Maharashtra, India
On Balanced Ternary

"Binary computing succeeded not because it is optimal, but because silicon transistors happened to be easiest to make bistable. Carbon nanotubes do not have this constraint. CNFET devices are naturally three-state. It would be a missed opportunity not to build the computing stack that matches."

— Manish Jagdish Thatte, 2026
The Complete Stack

What Was Built

From a single transistor to a running operating system, every layer designed from first principles around balanced ternary.

Hardware (P1–P3, P6, P7)

Device to Processor

CNFET device, switching method, CVD fabrication, standard cell library, PANINI processor — SPICE verified.

Software (P4, P5)

Compiler & OS

ManiT compiler for T3ISA, THATTE-OS microkernel with scheduler, IRQ handler, privilege domains — compiled and running.

Storage (P8, P9)

Filesystem & Data Structures

TritFS trit-addressed filesystem, TritTrie ternary data structure — with 128-entry ASCII encoding table.