A Balanced Ternary Standard Cell Gate Library with Three-Rail VLSI Power Distribution Architecture

Overview

A standard cell gate library for balanced ternary VLSI design, comprising four fundamental gate types: TINV (ternary inverter), TMIN2 (2-input minimum), TMAX3 (3-input maximum), and TMAJ3 (3-input majority/median). All gates verified through SPICE simulation using the RAVAN compact model.

The library includes a three-rail power distribution architecture (VDD, GND, VSS) that enables natural ternary operation. These four gate types form a functionally complete set for balanced ternary logic, meaning any ternary Boolean function can be composed from them.

Gate Types

• TINV Ternary inverter — maps +1 to -1, 0 to 0, -1 to +1. Symmetric V_th at +/-0.3V verified.
• TMIN2 Ternary minimum of two inputs. Complete 9-entry truth table verified correct.
• TMAX3 Ternary maximum of three inputs. Complete 27-entry truth table verified correct.
• TMAJ3 Ternary majority/median of three inputs. 27/27 correct with median proof verified.

Key Claims

The patent protects the following design innovations:

• A functionally complete set of four balanced ternary standard cells for VLSI design
• A three-rail power distribution architecture (VDD/GND/VSS) for ternary IC design
• SPICE-verified gate characterization using the RAVAN compact model
• A ternary majority/median gate with proven correctness across all input combinations
• Standard cell specifications enabling automated ternary place-and-route

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