A Method of Implementing Balanced Ternary Logic Switching in a CNT-FET

Overview

A method for implementing balanced ternary logic switching using current-direction encoding in carbon nanotube field-effect transistors. The method maps the three trit states (+1, 0, -1) to measurable current directions: positive drain current for +1, near-zero current for 0, and negative drain current for -1.

This method patent complements the device patent (P1) by covering the operational principles — specifically how three distinct logic states are reliably encoded, detected, and maintained. The coaxial geometry of the THATTE device provides inherent noise reduction that ensures signal integrity across all three states.

Key Claims

The patent protects the following method steps and innovations:

• A method of encoding balanced ternary logic states via current direction in a CNT-FET
• Current-direction discrimination for three-state logic detection
• Noise reduction through coaxial shielding geometry for reliable state discrimination
• Symmetric threshold voltage switching for balanced positive and negative state transitions
• A method for maintaining state integrity under nanoscale noise conditions

Layer in the Stack

Device Physics & Cells. This method patent defines how the THATTE Structure (P1) operates at the physics level. The switching method described here is the basis for the gate library in P6.

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